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riscv-openocd
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Merge pull request #217 from riscv/disable_target64 

build with --disable-target64
This commit is contained in:
Tim Newsome 2018-02-26 12:06:47 -08:00 committed by GitHub
parent 3c1c6e059c 6b02ab4196
commit 9033d99491
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 7 additions and 6 deletions
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1
.travis.yml
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@ -30,6 +30,7 @@ matrix:
env:
- BUILD=i686-linux-gnu
- CFLAGS=-m32
- CONFIGURE_ARGS="--disable-target64"
- EXECUTABLE=openocd
compiler: clang
addons:

4
src/target/mips_m4k.c
View File

@ -702,7 +702,7 @@ static int mips_m4k_set_breakpoint(struct target *target,
}
if (verify == 0) {
LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx64
LOG_ERROR("Unable to set 32bit breakpoint at address %08" TARGET_PRIxADDR
" - check that memory is read/writable", breakpoint->address);
return ERROR_OK;
}
@ -723,7 +723,7 @@ static int mips_m4k_set_breakpoint(struct target *target,
return retval;
if (verify != MIPS16_SDBBP(isa_req)) {
LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx64
LOG_ERROR("Unable to set 16bit breakpoint at address %08" TARGET_PRIxADDR
" - check that memory is read/writable", breakpoint->address);
return ERROR_OK;
}

8
src/target/riscv/riscv-013.c
View File

@ -795,12 +795,12 @@ static int examine_progbuf(struct target *target)
uint32_t written = dmi_read(target, DMI_PROGBUF0);
if (written == (uint32_t) info->progbuf_address) {
LOG_INFO("progbuf is writable at 0x%" TARGET_PRIxADDR,
LOG_INFO("progbuf is writable at 0x%" PRIx64,
info->progbuf_address);
info->progbuf_writable = YNM_YES;
} else {
LOG_INFO("progbuf is not writeable at 0x%" TARGET_PRIxADDR,
LOG_INFO("progbuf is not writeable at 0x%" PRIx64,
info->progbuf_address);
info->progbuf_writable = YNM_NO;
}
@ -1746,8 +1746,8 @@ static int read_memory_progbuf(struct target *target, target_addr_t address,
* dm_data0 contains mem[s0 - 2*size]
* s1 contains mem[s0-size] */
LOG_DEBUG("creating burst to read from 0x%" TARGET_PRIxADDR
" up to 0x%" TARGET_PRIxADDR, read_addr, fin_addr);
LOG_DEBUG("creating burst to read from 0x%" PRIx64
" up to 0x%" PRIx64, read_addr, fin_addr);
assert(read_addr >= address && read_addr < fin_addr);
struct riscv_batch *batch = riscv_batch_alloc(target, 32,
info->dmi_busy_delay + info->ac_busy_delay);