Merge pull request #191 from riscv/scanbuild

Fix some niggles found by clang's static analysis.

src/flash/nor/fespi.c

@@ -796,7 +796,6 @@ static int steps_execute(struct algorithm_steps *as,
 	struct target *target = bank->target;
 	struct fespi_flash_bank *fespi_info = bank->driver_priv;
 	uint32_t ctrl_base = fespi_info->ctrl_base;
-	uint8_t *data_buf = malloc(data_wa->size);
 	int xlen = riscv_xlen(target);
 
 	struct reg_param reg_params[2];
@@ -806,9 +805,11 @@ static int steps_execute(struct algorithm_steps *as,
 	buf_set_u64(reg_params[1].value, 0, xlen, data_wa->address);
 	while (!as_empty(as)) {
 		keep_alive();
+		uint8_t *data_buf = malloc(data_wa->size);
 		unsigned bytes = as_compile(as, data_buf, data_wa->size);
 		int retval = target_write_buffer(target, data_wa->address, bytes,
 				data_buf);
+		free(data_buf);
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Failed to write data to 0x%" TARGET_PRIxADDR ": %d",
 					data_wa->address, retval);

src/rtos/riscv_debug.c

@@ -279,7 +279,9 @@ static int riscv_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char
 	ssize_t hex_reg_list_length = n_regs * reg_chars + 2;
 	*hex_reg_list = malloc(hex_reg_list_length);
 	*hex_reg_list[0] = '\0';
+	char *p = hex_reg_list[0];
 	for (size_t i = 0; i < n_regs; ++i) {
+		assert(p - hex_reg_list[0] > 3);
 		if (riscv_has_register(rtos->target, thread_id, i)) {
 			uint64_t reg_value;
 			int result = riscv_get_register_on_hart(rtos->target, &reg_value,
@@ -289,13 +291,13 @@ static int riscv_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char
 
 			for (size_t byte = 0; byte < xlen / 8; ++byte) {
 				uint8_t reg_byte = reg_value >> (byte * 8);
-				char hex[3] = {'x', 'x', 'x'};
-				snprintf(hex, 3, "%02x", reg_byte);
-				strncat(*hex_reg_list, hex, hex_reg_list_length);
+				p += snprintf(p, 3, "%02x", reg_byte);
 			}
 		} else {
-			for (size_t byte = 0; byte < xlen / 8; ++byte)
-				strncat(*hex_reg_list, "xx", hex_reg_list_length);
+			for (size_t byte = 0; byte < xlen / 8; ++byte) {
+				strcpy(p, "xx");
+				p += 2;
+			}
 		}
 	}
 	LOG_DEBUG("%s", *hex_reg_list);

src/target/riscv/riscv-011.c

@@ -436,7 +436,7 @@ static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in,
 	int retval = jtag_execute_queue();
 	if (retval != ERROR_OK) {
 		LOG_ERROR("dbus_scan failed jtag scan");
-		return retval;
+		return DBUS_STATUS_FAILED;
 	}
 
 	if (data_in)
@@ -466,6 +466,10 @@ static uint64_t dbus_read(struct target *target, uint16_t address)
 		status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0);
 		if (status == DBUS_STATUS_BUSY)
 			increase_dbus_busy_delay(target);
+		if (status == DBUS_STATUS_FAILED) {
+			LOG_ERROR("dbus_read(0x%x) failed!", address);
+			return 0;
+		}
 	} while (((status == DBUS_STATUS_BUSY) || (address_in != address)) &&
 			i++ < 256);
 
@@ -675,6 +679,9 @@ static bits_t read_bits(struct target *target)
 					return err_result;
 				}
 				increase_dbus_busy_delay(target);
+			} else if (status == DBUS_STATUS_FAILED) {
+				// TODO: return an actual error
+				return err_result;
 			}
 		} while (status == DBUS_STATUS_BUSY && i++ < 256);
 
@@ -860,6 +867,7 @@ static int cache_write(struct target *target, unsigned int address, bool run)
 
 	int retval = scans_execute(scans);
 	if (retval != ERROR_OK) {
+		scans_delete(scans);
 		LOG_ERROR("JTAG execute failed.");
 		return retval;
 	}
@@ -873,12 +881,14 @@ static int cache_write(struct target *target, unsigned int address, bool run)
 				break;
 			case DBUS_STATUS_FAILED:
 				LOG_ERROR("Debug RAM write failed. Hardware error?");
+				scans_delete(scans);
 				return ERROR_FAIL;
 			case DBUS_STATUS_BUSY:
 				errors++;
 				break;
 			default:
 				LOG_ERROR("Got invalid bus access status: %d", status);
+				scans_delete(scans);
 				return ERROR_FAIL;
 		}
 	}
@@ -901,6 +911,7 @@ static int cache_write(struct target *target, unsigned int address, bool run)
 		if (wait_for_debugint_clear(target, true) != ERROR_OK) {
 			LOG_ERROR("Debug interrupt didn't clear.");
 			dump_debug_ram(target);
+			scans_delete(scans);
 			return ERROR_FAIL;
 		}
 
@@ -921,6 +932,7 @@ static int cache_write(struct target *target, unsigned int address, bool run)
 				if (wait_for_debugint_clear(target, false) != ERROR_OK) {
 					LOG_ERROR("Debug interrupt didn't clear.");
 					dump_debug_ram(target);
+					scans_delete(scans);
 					return ERROR_FAIL;
 				}
 			} else {
@@ -1804,14 +1816,14 @@ static riscv_error_t handle_halt_routine(struct target *target)
 	info->dpc = reg_cache_get(target, CSR_DPC);
 	info->dcsr = reg_cache_get(target, CSR_DCSR);
 
-	scans = scans_delete(scans);
+	scans_delete(scans);
 
 	cache_invalidate(target);
 
 	return RE_OK;
 
 error:
-	scans = scans_delete(scans);
+	scans_delete(scans);
 	return RE_FAIL;
 }
 
@@ -2271,6 +2283,7 @@ static int write_memory(struct target *target, target_addr_t address,
 		goto error;
 	}
 
+	scans_delete(scans);
 	cache_clean(target);
 	return register_write(target, T0, t0);
 

src/target/riscv/riscv-013.c

@@ -436,8 +436,12 @@ static uint64_t dmi_read(struct target *target, uint16_t address)
 	}
 
 	if (status != DMI_STATUS_SUCCESS) {
-		LOG_ERROR("Failed read (NOP) from 0x%x; value=0x%" PRIx64 ", status=%d",
-				address, value, status);
+		if (status == DMI_STATUS_FAILED) {
+			LOG_ERROR("Failed read (NOP) from 0x%x; status=%d", address, status);
+		} else {
+			LOG_ERROR("Failed read (NOP) from 0x%x; value=0x%" PRIx64 ", status=%d",
+					address, value, status);
+		}
 		return ~0ULL;
 	}
 
@@ -985,8 +989,6 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
 	if (result != ERROR_OK) {
 		assert(number != GDB_REGNO_S0);
 
-		result = ERROR_OK;
-
 		struct riscv_program program;
 		riscv_program_init(&program, target);
 
@@ -1653,7 +1655,6 @@ static int read_memory(struct target *target, target_addr_t address,
 		goto error;
 	write_to_buf(buffer + receive_addr - address, value, size);
 	LOG_DEBUG("M[0x%" TARGET_PRIxADDR "] reads 0x%" PRIx64, receive_addr, value);
-	receive_addr += size;
 
 	riscv_set_register(target, GDB_REGNO_S0, s0);
 	riscv_set_register(target, GDB_REGNO_S1, s1);