Merge pull request #116 from riscv/multigdb
Fix trigger code to work with multi-gdb mode instead of RTOS mode
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a3c26250bf
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@ -1718,7 +1718,7 @@ struct target_type riscv013_target =
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/*** 0.13-specific implementations of various RISC-V helper functions. ***/
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static riscv_reg_t riscv013_get_register(struct target *target, int hid, int rid)
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{
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LOG_DEBUG("reading register 0x%08x on hart %d", rid, hid);
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LOG_DEBUG("reading register %s on hart %d", gdb_regno_name(rid), hid);
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riscv_set_current_hartid(target, hid);
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@ -1750,7 +1750,8 @@ static riscv_reg_t riscv013_get_register(struct target *target, int hid, int rid
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static void riscv013_set_register(struct target *target, int hid, int rid, uint64_t value)
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{
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LOG_DEBUG("writing register 0x%08x on hart %d", rid, hid);
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LOG_DEBUG("writing 0x%" PRIx64 " to register %s on hart %d", value,
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gdb_regno_name(rid), hid);
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riscv_set_current_hartid(target, hid);
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@ -394,31 +394,43 @@ static int add_trigger(struct target *target, struct trigger *trigger)
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{
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RISCV_INFO(r);
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// In RTOS mode, we need to set the same trigger in the same slot on every
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// hart, to keep up the illusion that each hart is a thread running on the
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// same core.
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// Otherwise, we just set the trigger on the one hart this target deals
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// with.
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riscv_reg_t tselect[RISCV_MAX_HARTS];
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int first_hart = -1;
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for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
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if (!riscv_hart_enabled(target, hartid))
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continue;
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if (first_hart < 0)
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first_hart = hartid;
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tselect[hartid] = riscv_get_register_on_hart(target, hartid,
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GDB_REGNO_TSELECT);
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}
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assert(first_hart >= 0);
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unsigned int i;
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for (i = 0; i < r->trigger_count[0]; i++) {
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for (i = 0; i < r->trigger_count[first_hart]; i++) {
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if (r->trigger_unique_id[i] != -1) {
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continue;
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}
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riscv_set_register_on_hart(target, 0, GDB_REGNO_TSELECT, i);
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riscv_set_register_on_hart(target, first_hart, GDB_REGNO_TSELECT, i);
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uint64_t tdata1 = riscv_get_register_on_hart(target, 0, GDB_REGNO_TDATA1);
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uint64_t tdata1 = riscv_get_register_on_hart(target, first_hart, GDB_REGNO_TDATA1);
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int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
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int result = ERROR_OK;
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for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
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for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
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LOG_DEBUG(">>> hartid=%d", hartid);
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if (!riscv_hart_enabled(target, hartid))
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continue;
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if (hartid > 0) {
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if (hartid > first_hart) {
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, i);
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}
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switch (type) {
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@ -448,14 +460,14 @@ static int add_trigger(struct target *target, struct trigger *trigger)
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break;
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}
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for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
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for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
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if (!riscv_hart_enabled(target, hartid))
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continue;
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT,
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tselect[hartid]);
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}
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if (i >= r->trigger_count[0]) {
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if (i >= r->trigger_count[first_hart]) {
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LOG_ERROR("Couldn't find an available hardware trigger.");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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@ -507,19 +519,30 @@ static int remove_trigger(struct target *target, struct trigger *trigger)
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{
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RISCV_INFO(r);
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int first_hart = -1;
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for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
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if (!riscv_hart_enabled(target, hartid))
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continue;
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if (first_hart < 0) {
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first_hart = hartid;
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break;
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}
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}
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assert(first_hart >= 0);
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unsigned int i;
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for (i = 0; i < r->trigger_count[0]; i++) {
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for (i = 0; i < r->trigger_count[first_hart]; i++) {
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if (r->trigger_unique_id[i] == trigger->unique_id) {
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break;
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}
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}
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if (i >= r->trigger_count[0]) {
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if (i >= r->trigger_count[first_hart]) {
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LOG_ERROR("Couldn't find the hardware resources used by hardware "
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"trigger.");
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return ERROR_FAIL;
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}
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LOG_DEBUG("Stop using resource %d for bp %d", i, trigger->unique_id);
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for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
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for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
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if (!riscv_hart_enabled(target, hartid))
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continue;
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riscv_reg_t tselect = riscv_get_register_on_hart(target, hartid, GDB_REGNO_TSELECT);
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@ -67,7 +67,9 @@ typedef struct {
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unsigned trigger_count[RISCV_MAX_HARTS];
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/* For each physical trigger, contains -1 if the hwbp is available, or the
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* unique_id of the breakpoint/watchpoint that is using it. */
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* unique_id of the breakpoint/watchpoint that is using it.
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* Note that in RTOS mode the triggers are the same across all harts the
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* target controls, while otherwise only a single hart is controlled. */
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int trigger_unique_id[RISCV_MAX_HWBPS];
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/* The address of the debug RAM buffer. */
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