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riscv-openocd
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Update DMI bus width for 0.13. 

Change-Id: Ieff13a7a0084fe822b7cc6d927727eba4f158ef0
This commit is contained in:
Tim Newsome 2017-02-07 11:28:50 -08:00
parent d78ee9303e
commit 8af4a9a053
2 changed files with 2 additions and 10 deletions
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4
src/target/riscv/riscv-011.c
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@ -1442,10 +1442,6 @@ static int init_target(struct command_context *cmd_ctx,
return ERROR_FAIL;
riscv011_info_t *info = get_info(target);
select_dtmcontrol.num_bits = target->tap->ir_length;
select_dbus.num_bits = target->tap->ir_length;
select_idcode.num_bits = target->tap->ir_length;
target->reg_cache = calloc(1, sizeof(*target->reg_cache));
target->reg_cache->name = "RISC-V registers";
target->reg_cache->num_regs = REG_COUNT;

8
src/target/riscv/riscv-013.c
View File

@ -108,8 +108,8 @@ typedef enum {
DBUS_STATUS_BUSY = 3
} dbus_status_t;
#define DBUS_DATA_START 2
#define DBUS_DATA_SIZE 34
#define DBUS_ADDRESS_START 36
#define DBUS_DATA_SIZE 32
#define DBUS_ADDRESS_START 34
typedef enum {
RE_OK,
@ -1442,10 +1442,6 @@ static int init_target(struct command_context *cmd_ctx,
return ERROR_FAIL;
riscv013_info_t *info = get_info(target);
select_dtmcontrol.num_bits = target->tap->ir_length;
select_dbus.num_bits = target->tap->ir_length;
select_idcode.num_bits = target->tap->ir_length;
target->reg_cache = calloc(1, sizeof(*target->reg_cache));
target->reg_cache->name = "RISC-V registers";
target->reg_cache->num_regs = REG_COUNT;