Disable debugger-set triggers on connect
When first connecting to a target, have the debugger disable any hardware triggers that are set by a previously connected debugger. The 0.11 code already did this, but 0.13 did not. To achieve this I decided to share the code to enumerate triggers between 0.11 and 0.13, which required me to implement get_register() and set_register() for 0.11, which made the whole change a lot larger than you might have guessed. Hopefully this sets us up to in the future share the code to set/remove triggers as well.
This commit is contained in:
Tim Newsome
parent
29b62710f7
commit
4072fa493b
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@ -216,8 +216,6 @@ typedef struct {
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// unique_id of the breakpoint/watchpoint that is using it.
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int trigger_unique_id[MAX_HWBPS];
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unsigned int trigger_count;
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// Number of run-test/idle cycles the target requests we do after each dbus
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// access.
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unsigned int dtmcontrol_idle;
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@ -1045,7 +1043,7 @@ static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
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uint32_t exception = cache_get32(target, info->dramsize-1);
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if (exception) {
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LOG_ERROR("Got exception 0x%x when reading CSR 0x%x", exception, csr);
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LOG_WARNING("Got exception 0x%x when reading CSR 0x%x", exception, csr);
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*value = ~0;
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return ERROR_FAIL;
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}
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@ -1260,22 +1258,54 @@ static int update_mstatus_actual(struct target *target)
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/*** OpenOCD target functions. ***/
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static int register_read(struct target *target, riscv_reg_t *value, int regnum)
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{
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riscv011_info_t *info = get_info(target);
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if (regnum >= REG_CSR0 && regnum <= REG_CSR4095) {
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cache_set32(target, 0, csrr(S0, regnum - REG_CSR0));
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cache_set_store(target, 1, S0, SLOT0);
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cache_set_jump(target, 2);
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} else {
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LOG_ERROR("Don't know how to read register %d", regnum);
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return ERROR_FAIL;
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}
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if (cache_write(target, 4, true) != ERROR_OK) {
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return ERROR_FAIL;
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}
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uint32_t exception = cache_get32(target, info->dramsize-1);
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if (exception) {
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LOG_WARNING("Got exception 0x%x when reading register %d", exception,
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regnum);
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*value = ~0;
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return ERROR_FAIL;
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}
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*value = cache_get(target, SLOT0);
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LOG_DEBUG("reg[%d]=0x%" PRIx64, regnum, *value);
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if (regnum == REG_MSTATUS) {
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info->mstatus_actual = *value;
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}
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return ERROR_OK;
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}
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static int register_get(struct reg *reg)
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{
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struct target *target = (struct target *) reg->arch_info;
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riscv011_info_t *info = get_info(target);
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maybe_write_tselect(target);
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riscv_reg_t value = ~0;
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if (reg->number <= REG_XPR31) {
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buf_set_u64(reg->value, 0, riscv_xlen(target), reg_cache_get(target, reg->number));
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value = reg_cache_get(target, reg->number);
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LOG_DEBUG("%s=0x%" PRIx64, reg->name, reg_cache_get(target, reg->number));
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return ERROR_OK;
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} else if (reg->number == REG_PC) {
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buf_set_u32(reg->value, 0, 32, info->dpc);
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reg->valid = true;
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value = info->dpc;
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LOG_DEBUG("%s=0x%" PRIx64 " (cached)", reg->name, info->dpc);
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return ERROR_OK;
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} else if (reg->number >= REG_FPR0 && reg->number <= REG_FPR31) {
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int result = update_mstatus_actual(target);
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if (result != ERROR_OK) {
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@ -1295,44 +1325,24 @@ static int register_get(struct reg *reg)
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cache_set32(target, i++, fsd(reg->number - REG_FPR0, 0, DEBUG_RAM_START + 16));
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}
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cache_set_jump(target, i++);
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} else if (reg->number >= REG_CSR0 && reg->number <= REG_CSR4095) {
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cache_set32(target, 0, csrr(S0, reg->number - REG_CSR0));
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cache_set_store(target, 1, S0, SLOT0);
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cache_set_jump(target, 2);
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} else if (reg->number == REG_PRIV) {
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buf_set_u64(reg->value, 0, 8, get_field(info->dcsr, DCSR_PRV));
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LOG_DEBUG("%s=%d (cached)", reg->name,
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(int) get_field(info->dcsr, DCSR_PRV));
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return ERROR_OK;
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if (cache_write(target, 4, true) != ERROR_OK) {
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return ERROR_FAIL;
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}
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} else {
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LOG_ERROR("Don't know how to read register %d (%s)", reg->number, reg->name);
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return ERROR_FAIL;
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if (register_read(target, &value, reg->number) != ERROR_OK)
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return ERROR_FAIL;
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}
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if (cache_write(target, 4, true) != ERROR_OK) {
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return ERROR_FAIL;
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}
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uint32_t exception = cache_get32(target, info->dramsize-1);
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if (exception) {
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LOG_ERROR("Got exception 0x%x when reading register %d", exception,
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reg->number);
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buf_set_u64(reg->value, 0, riscv_xlen(target), ~0);
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return ERROR_FAIL;
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}
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uint64_t value = cache_get(target, SLOT0);
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LOG_DEBUG("%s=0x%" PRIx64, reg->name, value);
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buf_set_u64(reg->value, 0, riscv_xlen(target), value);
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if (reg->number == REG_MSTATUS) {
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info->mstatus_actual = value;
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reg->valid = true;
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}
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return ERROR_OK;
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}
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// Write the register. No caching or games.
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static int register_write(struct target *target, unsigned int number,
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uint64_t value)
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{
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@ -1396,7 +1406,7 @@ static int register_write(struct target *target, unsigned int number,
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uint32_t exception = cache_get32(target, info->dramsize-1);
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if (exception) {
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LOG_ERROR("Got exception 0x%x when writing register %d", exception,
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LOG_WARNING("Got exception 0x%x when writing register %d", exception,
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number);
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return ERROR_FAIL;
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}
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@ -1423,6 +1433,25 @@ static struct reg_arch_type riscv_reg_arch_type = {
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.set = register_set
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};
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static riscv_reg_t get_register(struct target *target, int hartid, int regid)
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{
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assert(hartid == 0);
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riscv_reg_t value;
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if (register_read(target, &value, regid) != ERROR_OK) {
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// TODO: propagate errors
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value = ~0;
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}
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return value;
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}
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static void set_register(struct target *target, int hartid, int regid,
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uint64_t value)
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{
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assert(hartid == 0);
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// TODO: propagate errors
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register_write(target, regid, value);
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}
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static int halt(struct target *target)
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{
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LOG_DEBUG("riscv_halt()");
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@ -1446,7 +1475,8 @@ static int init_target(struct command_context *cmd_ctx,
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{
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LOG_DEBUG("init");
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riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
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generic_info->get_register = NULL;
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generic_info->get_register = get_register;
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generic_info->set_register = set_register;
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generic_info->version_specific = calloc(1, sizeof(riscv011_info_t));
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if (!generic_info->version_specific)
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return ERROR_FAIL;
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@ -1605,11 +1635,12 @@ static int maybe_add_trigger_t2(struct target *target, struct trigger *trigger,
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static int add_trigger(struct target *target, struct trigger *trigger)
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{
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riscv011_info_t *info = get_info(target);
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RISCV_INFO(r);
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maybe_read_tselect(target);
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unsigned int i;
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for (i = 0; i < info->trigger_count; i++) {
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for (i = 0; i < r->trigger_count[0]; i++) {
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if (info->trigger_unique_id[i] != -1) {
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continue;
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}
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@ -1642,7 +1673,7 @@ static int add_trigger(struct target *target, struct trigger *trigger)
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info->trigger_unique_id[i] = trigger->unique_id;
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break;
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}
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if (i >= info->trigger_count) {
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if (i >= r->trigger_count[0]) {
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LOG_ERROR("Couldn't find an available hardware trigger.");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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@ -1652,17 +1683,18 @@ static int add_trigger(struct target *target, struct trigger *trigger)
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static int remove_trigger(struct target *target, struct trigger *trigger)
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{
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RISCV_INFO(r);
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riscv011_info_t *info = get_info(target);
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maybe_read_tselect(target);
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unsigned int i;
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for (i = 0; i < info->trigger_count; i++) {
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for (i = 0; i < r->trigger_count[0]; i++) {
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if (info->trigger_unique_id[i] == trigger->unique_id) {
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break;
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}
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}
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if (i >= info->trigger_count) {
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if (i >= r->trigger_count[0]) {
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LOG_ERROR("Couldn't find the hardware resources used by hardware "
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"trigger.");
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return ERROR_FAIL;
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@ -2200,30 +2232,10 @@ static int handle_halt(struct target *target, bool announce)
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if (info->never_halted) {
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info->never_halted = false;
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// Disable any hardware triggers that have dmode set. We can't have set
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// them ourselves. Maybe they're left over from some killed debug
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// session.
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// Count the number of triggers while we're at it.
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int result = maybe_read_tselect(target);
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if (result != ERROR_OK)
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return result;
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for (info->trigger_count = 0; info->trigger_count < MAX_HWBPS; info->trigger_count++) {
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write_csr(target, CSR_TSELECT, info->trigger_count);
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uint64_t tselect_rb;
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read_csr(target, &tselect_rb, CSR_TSELECT);
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// Mask off the top bit, which is used as tdrmode in old
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// implementations.
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tselect_rb &= ~(1ULL << (riscv_xlen(target)-1));
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if (info->trigger_count != tselect_rb)
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break;
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uint64_t tdata1;
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read_csr(target, &tdata1, CSR_TDATA1);
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if ((tdata1 & MCONTROL_DMODE(riscv_xlen(target))) &&
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(tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD))) {
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write_csr(target, CSR_TDATA1, 0);
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}
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}
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riscv_enumerate_triggers(target);
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}
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if (announce) {
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@ -1239,21 +1239,7 @@ static int examine(struct target *target)
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}
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/* Then we check the number of triggers availiable to each hart. */
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for (int i = 0; i < riscv_count_harts(target); ++i) {
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if (!riscv_hart_enabled(target, i))
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continue;
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for (uint32_t t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
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riscv_set_current_hartid(target, i);
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r->trigger_count[i] = t;
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register_write_direct(target, GDB_REGNO_TSELECT, t);
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uint64_t tselect = t+1;
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register_read_direct(target, &tselect, GDB_REGNO_TSELECT);
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if (tselect != t)
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break;
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}
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}
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riscv_enumerate_triggers(target);
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/* Resumes all the harts, so the debugger can later pause them. */
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riscv_resume_all_harts(target);
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@ -1103,10 +1103,12 @@ void riscv_set_register(struct target *target, enum gdb_regno r, riscv_reg_t v)
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return riscv_set_register_on_hart(target, riscv_current_hartid(target), r, v);
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}
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void riscv_set_register_on_hart(struct target *target, int hartid, enum gdb_regno regid, uint64_t value)
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void riscv_set_register_on_hart(struct target *target, int hartid,
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enum gdb_regno regid, uint64_t value)
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{
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RISCV_INFO(r);
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LOG_DEBUG("writing register %d on hart %d", regid, hartid);
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LOG_DEBUG("[%d] reg[%d] <- %" PRIx64, hartid, regid, value);
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assert(r->set_register);
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return r->set_register(target, hartid, regid, value);
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}
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@ -1243,3 +1245,53 @@ bool riscv_hart_enabled(struct target *target, int hartid)
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return hartid == target->coreid;
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}
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/**
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* Count triggers, and initialize trigger_count for each hart.
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* trigger_count is initialized even if this function fails to discover
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* something.
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* Disable any hardware triggers that have dmode set. We can't have set them
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* ourselves. Maybe they're left over from some killed debug session.
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* */
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int riscv_enumerate_triggers(struct target *target)
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{
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RISCV_INFO(r);
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for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
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if (!riscv_hart_enabled(target, hartid))
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continue;
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for (unsigned t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
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r->trigger_count[hartid] = t;
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, t);
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uint64_t tselect = riscv_get_register_on_hart(target, hartid,
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GDB_REGNO_TSELECT);
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// Mask off the top bit, which is used as tdrmode in old
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// implementations.
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tselect &= ~(1ULL << (riscv_xlen(target)-1));
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if (tselect != t)
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break;
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uint64_t tdata1 = riscv_get_register_on_hart(target, hartid,
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GDB_REGNO_TDATA1);
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int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
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switch (type) {
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case 1:
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// On these older cores we don't support software using
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// triggers.
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
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break;
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case 2:
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if (tdata1 & MCONTROL_DMODE(riscv_xlen(target))) {
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
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}
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break;
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}
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}
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LOG_DEBUG("[%d] Found %d triggers", hartid, r->trigger_count[hartid]);
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}
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return ERROR_OK;
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}
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@ -57,7 +57,7 @@ typedef struct {
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int xlen[RISCV_MAX_HARTS];
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/* The number of triggers per hart. */
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int trigger_count[RISCV_MAX_HARTS];
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unsigned trigger_count[RISCV_MAX_HARTS];
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/* The address of the debug RAM buffer. */
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riscv_addr_t debug_buffer_addr[RISCV_MAX_HARTS];
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@ -70,8 +70,9 @@ typedef struct {
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/* Helper functions that target the various RISC-V debug spec
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* implementations. */
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riscv_reg_t (*get_register)(struct target *, int, int);
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void (*set_register)(struct target *, int, int, uint64_t);
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riscv_reg_t (*get_register)(struct target *, int hartid, int regid);
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void (*set_register)(struct target *, int hartid, int regid,
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uint64_t value);
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void (*select_current_hart)(struct target *);
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bool (*is_halted)(struct target *target);
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void (*halt_current_hart)(struct target *);
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@ -218,4 +219,6 @@ void riscv_invalidate_register_cache(struct target *target);
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/* Returns TRUE when a hart is enabled in this target. */
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bool riscv_hart_enabled(struct target *target, int hartid);
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int riscv_enumerate_triggers(struct target *target);
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#endif
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