Flash at 8KB/s, using 10,000 byte working area.
If the working area is large enough, every fespi_write() results in just a single algorithm execution. Change-Id: I87a12e29f50ef6ea1f46fbd1edf440f9e54a2162
This commit is contained in:
Tim Newsome
parent
1551916027
commit
8ee0647365
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@ -16,7 +16,7 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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/* The Freedeom E SPI controller is a SPI bus controller
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/* The Freedem E SPI controller is a SPI bus controller
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* specifically designed for SPI Flash Memories on Freedom E platforms.
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*
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* Two working modes are available:
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@ -28,7 +28,7 @@
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/* ATTENTION:
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* To have flash memory mapped in CPU memory space, the controller
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* has have "HW mode" enabled.
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* must have "HW mode" enabled.
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* 1) The command "reset init" has to initialize the controller and put
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* it in HW mode (this is actually the default out of reset for Freedom E systems).
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* 2) every command in this file have to return to prompt in HW mode. */
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@ -251,7 +251,6 @@ static int fespi_wip (struct flash_bank * bank, int timeout)
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fespi_rx(bank);
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do {
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alive_sleep(1);
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fespi_tx(bank, 0);
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@ -260,7 +259,6 @@ static int fespi_wip (struct flash_bank * bank, int timeout)
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fespi_set_dir(bank, FESPI_DIR_TX);
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return ERROR_OK;
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}
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} while (timeval_ms() < endtime);
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LOG_ERROR("timeout");
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@ -386,6 +384,8 @@ static int slow_fespi_write_buffer(struct flash_bank *bank,
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FESPI_WRITE_REG(FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
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keep_alive();
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return ERROR_OK;
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}
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@ -398,12 +398,18 @@ static int slow_fespi_write_buffer(struct flash_bank *bank,
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xxd -i algorithm.bin
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// ALGO_START
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#define SPIFLASH_READ_STATUS 0x05 // Read Status Register
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#define SPIFLASH_BSY_BIT 0x00000001 // WIP Bit of SPI SR on SMI SR
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// Register offsets
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#define FESPI_REG_FMT 0x40
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#define FESPI_REG_TXFIFO 0x48
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#define FESPI_REG_RXFIFO 0x4c
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#define FESPI_REG_IP 0x74
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// Fields
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#define FESPI_IP_TXWM 0x1
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#define FESPI_FMT_DIR(x) (((x) & 0x1) << 3)
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// To enter, jump to the start of command_table (ie. offset 0).
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// a0 - FESPI base address
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@ -414,6 +420,7 @@ static int slow_fespi_write_buffer(struct flash_bank *bank,
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// the program, while some will not. The operation byte is the offset into
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// command_table, so eg. 4 means exit, 8 means transmit, and so on.
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.global _start
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_start:
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command_table:
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j main // 0
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@ -421,6 +428,8 @@ command_table:
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j tx // 8
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j txwm_wait // 12
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j write_reg // 16
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j wip_wait // 20
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j set_dir // 24
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// Execute the program.
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main:
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@ -460,25 +469,63 @@ write_reg:
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addi a1, a1, 2
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sw t1, 0(t0)
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j main
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wip_wait:
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li a2, SPIFLASH_READ_STATUS
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jal txrx_byte
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// discard first result
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1: li a2, 0
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jal txrx_byte
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andi t0, a2, SPIFLASH_BSY_BIT
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bnez t0, 1b
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j main
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txrx_byte: // transmit the byte in a2, receive a bit into a2
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lw t0, FESPI_REG_TXFIFO(a0) // wait for FIFO clear
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bltz t0, txrx_byte
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sw a2, FESPI_REG_TXFIFO(a0)
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1: lw a2, FESPI_REG_RXFIFO(a0)
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bltz a2, 1b
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ret
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set_dir:
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lw t0, FESPI_REG_FMT(a0)
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li t1, ~(FESPI_FMT_DIR(0xFFFFFFFF))
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and t0, t0, t1
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lbu t1, 0(a1) // read value to OR in
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addi a1, a1, 1
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or t0, t0, t1
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sw t0, FESPI_REG_FMT(a0)
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j main
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// ALGO_END
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*/
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static const uint8_t algorithm_bin[] = {
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0x6f, 0x00, 0x40, 0x01, 0x73, 0x00, 0x10, 0x00, 0x6f, 0x00, 0x40, 0x02,
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0x6f, 0x00, 0x80, 0x04, 0x6f, 0x00, 0x40, 0x05, 0x83, 0xc2, 0x05, 0x00,
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0x93, 0x85, 0x15, 0x00, 0x17, 0x03, 0x00, 0x00, 0x13, 0x03, 0x43, 0xfe,
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0xb3, 0x82, 0x62, 0x00, 0x67, 0x80, 0x02, 0x00, 0x03, 0xc3, 0x05, 0x00,
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0x93, 0x85, 0x15, 0x00, 0x83, 0x22, 0x85, 0x04, 0xe3, 0xce, 0x02, 0xfe,
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0x83, 0xc2, 0x05, 0x00, 0x23, 0x24, 0x55, 0x04, 0x93, 0x85, 0x15, 0x00,
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0x13, 0x03, 0xf3, 0xff, 0xe3, 0x44, 0x60, 0xfe, 0x6f, 0xf0, 0x5f, 0xfc,
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0x83, 0x22, 0x45, 0x07, 0x93, 0xf2, 0x12, 0x00, 0xe3, 0x8c, 0x02, 0xfe,
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0x6f, 0xf0, 0x5f, 0xfb, 0x83, 0xc2, 0x05, 0x00, 0xb3, 0x82, 0xa2, 0x00,
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0x03, 0xc3, 0x15, 0x00, 0x93, 0x85, 0x25, 0x00, 0x23, 0xa0, 0x62, 0x00,
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0x6f, 0xf0, 0xdf, 0xf9
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0x6f, 0x00, 0xc0, 0x01, 0x73, 0x00, 0x10, 0x00, 0x6f, 0x00, 0xc0, 0x02,
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0x6f, 0x00, 0x00, 0x05, 0x6f, 0x00, 0xc0, 0x05, 0x6f, 0x00, 0x00, 0x07,
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0x6f, 0x00, 0x00, 0x0a, 0x83, 0xc2, 0x05, 0x00, 0x93, 0x85, 0x15, 0x00,
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0x17, 0x03, 0x00, 0x00, 0x13, 0x03, 0xc3, 0xfd, 0xb3, 0x82, 0x62, 0x00,
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0x67, 0x80, 0x02, 0x00, 0x03, 0xc3, 0x05, 0x00, 0x93, 0x85, 0x15, 0x00,
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0x83, 0x22, 0x85, 0x04, 0xe3, 0xce, 0x02, 0xfe, 0x83, 0xc2, 0x05, 0x00,
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0x23, 0x24, 0x55, 0x04, 0x93, 0x85, 0x15, 0x00, 0x13, 0x03, 0xf3, 0xff,
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0xe3, 0x44, 0x60, 0xfe, 0x6f, 0xf0, 0x5f, 0xfc, 0x83, 0x22, 0x45, 0x07,
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0x93, 0xf2, 0x12, 0x00, 0xe3, 0x8c, 0x02, 0xfe, 0x6f, 0xf0, 0x5f, 0xfb,
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0x83, 0xc2, 0x05, 0x00, 0xb3, 0x82, 0xa2, 0x00, 0x03, 0xc3, 0x15, 0x00,
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0x93, 0x85, 0x25, 0x00, 0x23, 0xa0, 0x62, 0x00, 0x6f, 0xf0, 0xdf, 0xf9,
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0x13, 0x06, 0x50, 0x00, 0xef, 0x00, 0x80, 0x01, 0x13, 0x06, 0x00, 0x00,
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0xef, 0x00, 0x00, 0x01, 0x93, 0x72, 0x16, 0x00, 0xe3, 0x9a, 0x02, 0xfe,
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0x6f, 0xf0, 0x1f, 0xf8, 0x83, 0x22, 0x85, 0x04, 0xe3, 0xce, 0x02, 0xfe,
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0x23, 0x24, 0xc5, 0x04, 0x03, 0x26, 0xc5, 0x04, 0xe3, 0x4e, 0x06, 0xfe,
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0x67, 0x80, 0x00, 0x00, 0x83, 0x22, 0x05, 0x04, 0x13, 0x03, 0x70, 0xff,
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0xb3, 0xf2, 0x62, 0x00, 0x03, 0xc3, 0x05, 0x00, 0x93, 0x85, 0x15, 0x00,
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0xb3, 0xe2, 0x62, 0x00, 0x23, 0x20, 0x55, 0x04, 0x6f, 0xf0, 0x9f, 0xf4
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};
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#define STEP_EXIT 4
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#define STEP_TX 8
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#define STEP_TXWM_WAIT 12
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#define STEP_WRITE_REG 16
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#define STEP_WIP_WAIT 20
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#define STEP_SET_DIR 24
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#define STEP_NOP 0xff
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struct algorithm_steps {
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@ -519,32 +566,53 @@ unsigned as_compile(struct algorithm_steps *as, uint8_t *target,
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unsigned target_size)
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{
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unsigned offset = 0;
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for (unsigned s = 0; s < as->used; s++) {
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bool finish_early = false;
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for (unsigned s = 0; s < as->used && !finish_early; s++) {
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unsigned bytes_left = target_size - offset;
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switch (as->steps[s][0]) {
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case STEP_NOP:
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break;
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case STEP_TX:
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{
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unsigned size = as->steps[s][1];
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assert(offset + size + 3 < target_size);
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if (size + 3 > bytes_left) {
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finish_early = true;
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break;
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}
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memcpy(target + offset, as->steps[s], size + 2);
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offset += size + 2;
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break;
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}
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case STEP_WRITE_REG:
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assert(offset + 3 < target_size);
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if (4 > bytes_left) {
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finish_early = true;
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break;
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}
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memcpy(target + offset, as->steps[s], 3);
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offset += 3;
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break;
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case STEP_SET_DIR:
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if (3 > bytes_left) {
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finish_early = true;
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break;
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}
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memcpy(target + offset, as->steps[s], 2);
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offset += 2;
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break;
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case STEP_TXWM_WAIT:
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assert(offset + 1 < target_size);
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case STEP_WIP_WAIT:
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if (2 > bytes_left) {
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finish_early = true;
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break;
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}
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memcpy(target + offset, as->steps[s], 1);
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offset += 1;
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break;
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default:
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assert(0);
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}
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as->steps[s][0] = STEP_NOP;
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if (!finish_early)
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as->steps[s][0] = STEP_NOP;
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}
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assert(offset + 1 < target_size);
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target[offset++] = STEP_EXIT;
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@ -602,39 +670,27 @@ void as_add_txwm_wait(struct algorithm_steps *as)
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as->used++;
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}
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/* This should write something less than or equal to a page.*/
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static int fespi_write_buffer(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t chip_offset, uint32_t len,
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struct working_area *algorithm_wa)
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void as_add_wip_wait(struct algorithm_steps *as)
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{
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struct target *target = bank->target;
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struct fespi_flash_bank *fespi_info = bank->driver_priv;
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uint32_t ctrl_base = fespi_info->ctrl_base;
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assert(as->used < as->size);
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as->steps[as->used] = malloc(1);
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as->steps[as->used][0] = STEP_WIP_WAIT;
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as->used++;
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}
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LOG_DEBUG("%s: chip_offset=0x%08" PRIx32 " len=0x%08" PRIx32,
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__func__, chip_offset, len);
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if (!algorithm_wa) {
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return slow_fespi_write_buffer(bank, buffer, chip_offset, len);
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}
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struct working_area *data_wa;
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unsigned data_wa_size = 2 * len;
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while (1) {
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if (data_wa_size < 128) {
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LOG_WARNING("Couldn't allocate data working area.");
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return slow_fespi_write_buffer(bank, buffer, chip_offset, len);
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}
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if (target_alloc_working_area_try(target, data_wa_size, &data_wa) ==
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ERROR_OK) {
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break;
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}
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data_wa_size /= 2;
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}
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struct algorithm_steps *as = as_new(100);
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void as_add_set_dir(struct algorithm_steps *as, bool dir)
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{
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assert(as->used < as->size);
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as->steps[as->used] = malloc(2);
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as->steps[as->used][0] = STEP_SET_DIR;
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as->steps[as->used][1] = FESPI_FMT_DIR(dir);
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as->used++;
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}
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/* This should write something less than or equal to a page.*/
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static int steps_add_buffer_write(struct algorithm_steps *as,
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const uint8_t *buffer, uint32_t chip_offset, uint32_t len)
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{
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as_add_tx1(as, SPIFLASH_WRITE_ENABLE);
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as_add_txwm_wait(as);
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as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
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@ -651,6 +707,23 @@ static int fespi_write_buffer(struct flash_bank *bank, const uint8_t *buffer,
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as_add_txwm_wait(as);
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as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
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// fespi_wip()
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as_add_set_dir(as, FESPI_DIR_RX);
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as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
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as_add_wip_wait(as);
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as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
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as_add_set_dir(as, FESPI_DIR_TX);
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return ERROR_OK;
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}
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static int steps_execute(struct algorithm_steps *as,
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struct flash_bank *bank, struct working_area *algorithm_wa,
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struct working_area *data_wa)
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{
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struct target *target = bank->target;
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struct fespi_flash_bank *fespi_info = bank->driver_priv;
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uint32_t ctrl_base = fespi_info->ctrl_base;
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uint8_t *data_buf = malloc(data_wa->size);
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struct reg_param reg_params[2];
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@ -659,13 +732,14 @@ static int fespi_write_buffer(struct flash_bank *bank, const uint8_t *buffer,
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buf_set_u32(reg_params[0].value, 0, 32, ctrl_base);
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buf_set_u32(reg_params[1].value, 0, 32, data_wa->address);
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while (!as_empty(as)) {
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keep_alive();
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unsigned bytes = as_compile(as, data_buf, data_wa->size);
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int retval = target_write_buffer(target, data_wa->address, bytes,
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data_buf);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to write data to 0x%x: %d", data_wa->address,
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retval);
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goto error;
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return retval;
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}
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retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
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@ -674,18 +748,11 @@ static int fespi_write_buffer(struct flash_bank *bank, const uint8_t *buffer,
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to execute algorithm at 0x%x: %d", algorithm_wa->address,
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retval);
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goto error;
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return retval;
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}
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}
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target_free_working_area(target, data_wa);
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return ERROR_OK;
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error:
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target_free_working_area(target, data_wa);
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LOG_ERROR("Falling back to slow write.");
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return slow_fespi_write_buffer(bank, buffer, chip_offset, len);
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}
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static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
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@ -741,6 +808,22 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
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}
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}
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struct working_area *data_wa = NULL;
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unsigned data_wa_size = 2 * count;
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while (1) {
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if (data_wa_size < 128) {
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LOG_WARNING("Couldn't allocate data working area.");
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target_free_working_area(target, algorithm_wa);
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algorithm_wa = NULL;
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}
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if (target_alloc_working_area_try(target, data_wa_size, &data_wa) ==
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ERROR_OK) {
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break;
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}
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data_wa_size /= 2;
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}
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page_size = fespi_info->dev->pagesize;
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fespi_txwm_wait(bank);
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@ -753,13 +836,18 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
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if (retval != ERROR_OK)
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return retval;
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struct algorithm_steps *as = as_new(count / 16);
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/* unaligned buffer head */
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if (count > 0 && (offset & 3) != 0) {
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cur_count = 4 - (offset & 3);
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if (cur_count > count)
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cur_count = count;
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retval = fespi_write_buffer(bank, buffer, offset,
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cur_count, algorithm_wa);
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if (algorithm_wa) {
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retval = steps_add_buffer_write(as, buffer, offset, cur_count);
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} else {
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retval = slow_fespi_write_buffer(bank, buffer, offset, cur_count);
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}
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if (retval != ERROR_OK)
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goto err;
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offset += cur_count;
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@ -776,8 +864,11 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
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else
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cur_count = count & ~3;
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retval = fespi_write_buffer(bank, buffer, offset,
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cur_count, algorithm_wa);
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if (algorithm_wa) {
|
||||
retval = steps_add_buffer_write(as, buffer, offset, cur_count);
|
||||
} else {
|
||||
retval = slow_fespi_write_buffer(bank, buffer, offset, cur_count);
|
||||
}
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
|
|
@ -785,16 +876,26 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
|
|||
buffer += cur_count;
|
||||
offset += cur_count;
|
||||
count -= cur_count;
|
||||
|
||||
keep_alive();
|
||||
}
|
||||
|
||||
/* buffer tail */
|
||||
if (count > 0)
|
||||
retval = fespi_write_buffer(bank, buffer, offset, count, algorithm_wa);
|
||||
if (count > 0) {
|
||||
if (algorithm_wa) {
|
||||
retval = steps_add_buffer_write(as, buffer, offset, count);
|
||||
} else {
|
||||
retval = slow_fespi_write_buffer(bank, buffer, offset, count);
|
||||
}
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (algorithm_wa) {
|
||||
retval = steps_execute(as, bank, algorithm_wa, data_wa);
|
||||
}
|
||||
|
||||
err:
|
||||
if (algorithm_wa) {
|
||||
target_free_working_area(target, data_wa);
|
||||
target_free_working_area(target, algorithm_wa);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2701,6 +2701,8 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
|
|||
int64_t now = timeval_ms();
|
||||
if (now - start > timeout_ms) {
|
||||
LOG_ERROR("Algorithm timed out after %d ms.", timeout_ms);
|
||||
riscv_halt(target);
|
||||
riscv_poll(target);
|
||||
return ERROR_TARGET_TIMEOUT;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue