Added address alignment test, code fixups from review
This commit is contained in:
Ryan Macdonald
parent
836bd7cb69
commit
cc98a14839
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@ -58,9 +58,11 @@ static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a);
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static int riscv013_dmi_write_u64_bits(struct target *target);
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static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf);
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static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address,
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target_addr_t illegal_address);
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uint32_t read_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t sbcs);
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void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t data, uint32_t sbcs);
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uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
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void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t* write_data,
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uint32_t write_size, uint32_t sbcs);
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uint32_t* read_memory_sba_simple(struct target *target, target_addr_t addr,
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uint32_t read_size, uint32_t sbcs);
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static int register_read_direct(struct target *target, uint64_t *value, uint32_t number);
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static int register_write_direct(struct target *target, unsigned number,
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uint64_t value);
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@ -2816,7 +2818,7 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
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buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0);
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}
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static uint32_t get_max_sbaccess(struct target *target)
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static int get_max_sbaccess(struct target *target)
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{
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RISCV013_INFO(info);
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@ -2840,8 +2842,24 @@ static uint32_t get_max_sbaccess(struct target *target)
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return -1;
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}
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static uint32_t get_num_sbdata_regs(struct target *target)
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{
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RISCV013_INFO(info);
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uint32_t sbaccess128 = get_field(info->sbcs, DMI_SBCS_SBACCESS128);
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uint32_t sbaccess64 = get_field(info->sbcs, DMI_SBCS_SBACCESS64);
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if(sbaccess128)
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return 4;
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else if(sbaccess64)
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return 2;
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else
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return 1;
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}
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static int riscv013_test_sba_config_reg(struct target *target,
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target_addr_t legal_address, target_addr_t illegal_address)
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target_addr_t legal_address, uint32_t num_words,
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target_addr_t illegal_address, bool run_sbbusyerror_test)
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{
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LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13");
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@ -2864,35 +2882,47 @@ static int riscv013_test_sba_config_reg(struct target *target,
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return ERROR_FAIL;
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}
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// Test 1: Simple write/read test, no address autoincrement
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uint32_t num_sbdata_regs = get_num_sbdata_regs(target);
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// Test 1: Simple write/read test
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test_passed = true;
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 0);
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dmi_write(target, DMI_SBCS, sbcs);
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uint32_t test_patterns[4] = {0xdeadbeef, 0xfeedbabe, 0x12345678, 0x08675309};
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for (uint32_t sbaccess = 0; sbaccess <= (uint32_t)max_sbaccess; sbaccess++) {
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sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess);
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dmi_write(target, DMI_SBCS, sbcs);
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for (int i = 0; i < 100; i++) {
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uint32_t compare_mask = (sbaccess == 0) ? 0xff :
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(sbaccess == 1) ? 0xffff : 0xffffffff;
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for (uint32_t i = 0; i < num_words; i++) {
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uint32_t addr = legal_address + (i << sbaccess);
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write_memory_sba_simple(target, addr, i, sbcs);
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uint32_t wr_data[num_sbdata_regs];
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for (uint32_t j = 0; j < num_sbdata_regs; j++)
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wr_data[j] = test_patterns[j] + i;
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write_memory_sba_simple(target, addr, wr_data, num_sbdata_regs, sbcs);
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}
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for (uint32_t i = 0; i < 100; i++) {
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for (uint32_t i = 0; i < num_words; i++) {
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uint32_t addr = legal_address + (i << sbaccess);
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uint32_t val = read_memory_sba_simple(target, addr, sbcs);
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if (i != val) {
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LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x, expected val = %d, read val = %d", addr, i, val);
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test_passed = false;
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uint32_t* val = read_memory_sba_simple(target, addr, num_sbdata_regs, sbcs);
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for (uint32_t j = 0; j < num_sbdata_regs; j++) {
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if (((test_patterns[j]+i)&compare_mask) != (val[j]&compare_mask)) {
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LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x, expected val = %x, read val = %x", addr, test_patterns[j]+i, val[j]);
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test_passed = false;
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}
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}
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free(val);
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}
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}
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if (test_passed)
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LOG_INFO("System Bus Access Test 1: Read/write test, no addr autoincrement PASSED");
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LOG_INFO("System Bus Access Test 1: Simple write/read test PASSED.");
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// Test 2: Simple write/read test, with address autoincrement
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uint32_t curr_addr;
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uint32_t prev_addr;
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// Test 2: Address autoincrement test
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target_addr_t curr_addr;
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target_addr_t prev_addr;
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test_passed = true;
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 1);
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dmi_write(target, DMI_SBCS, sbcs);
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@ -2904,12 +2934,12 @@ static int riscv013_test_sba_config_reg(struct target *target,
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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read_sbcs_nonbusy(target, &sbcs);
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curr_addr = legal_address;
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for (int i = 0; i < 100; i++) {
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for (uint32_t i = 0; i < num_words; i++) {
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prev_addr = curr_addr;
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read_sbcs_nonbusy(target, &sbcs);
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dmi_read(target, &curr_addr, DMI_SBADDRESS0);
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curr_addr = sb_read_address(target);
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if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && i != 0) {
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LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x", sbaccess);
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LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess);
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test_passed = false;
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}
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dmi_write(target, DMI_SBDATA0, i);
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@ -2924,110 +2954,109 @@ static int riscv013_test_sba_config_reg(struct target *target,
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dmi_write(target, DMI_SBCS, sbcs);
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dmi_read(target, &val, DMI_SBDATA0); // Dummy read to trigger first system bus read
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curr_addr = legal_address;
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for (uint32_t i = 0; i < 100; i++) {
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for (uint32_t i = 0; i < num_words; i++) {
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prev_addr = curr_addr;
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read_sbcs_nonbusy(target, &sbcs);
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dmi_read(target, &curr_addr, DMI_SBADDRESS0);
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curr_addr = sb_read_address(target);
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if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && i != 0) {
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LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x", sbaccess);
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LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess);
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test_passed = false;
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}
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dmi_read(target, &val, DMI_SBDATA0);
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read_sbcs_nonbusy(target, &sbcs);
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if (i != val) {
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LOG_ERROR("System Bus Access Test 2: Error reading autoincremented address, expected val = %d, read val = %d",i,val);
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LOG_ERROR("System Bus Access Test 2: Error reading auto-incremented address, expected val = %x, read val = %x",i,val);
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test_passed = false;
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}
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}
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}
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if (test_passed)
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LOG_INFO("System Bus Access Test 2: Read/write test, addr autoincrement PASSED");
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LOG_INFO("System Bus Access Test 2: Address auto-increment test PASSED.");
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// Test 3: Read from illegal address
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read_memory_sba_simple(target, illegal_address, sbcs_orig);
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uint32_t* illegal_addr_read = read_memory_sba_simple(target, illegal_address, 1, sbcs_orig);
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free(illegal_addr_read);
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dmi_read(target, &rd_val, DMI_SBCS);
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if (get_field(rd_val, DMI_SBCS_SBERROR) == 2) {
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LOG_INFO("System Bus Access Test 3: Illegal address read test PASSED");
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LOG_INFO("System Bus Access Test 3: Illegal address read test PASSED.");
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1);
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dmi_write(target, DMI_SBCS, sbcs);
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} else {
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LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED");
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LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED.");
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}
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// Test 4: Write to illegal address
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write_memory_sba_simple(target, illegal_address, 0xdeadbeef, sbcs_orig);
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write_memory_sba_simple(target, illegal_address, test_patterns, 1, sbcs_orig);
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dmi_read(target, &rd_val, DMI_SBCS);
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if (get_field(rd_val, DMI_SBCS_SBERROR) == 2) {
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LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED");
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LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED.");
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1);
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dmi_write(target, DMI_SBCS,sbcs);
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} else {
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LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED");
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LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED.");
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}
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// Test 5: Write to unsupported sbaccess size
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// Test 5: Write with unsupported sbaccess size
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uint32_t sbaccess128 = get_field(sbcs_orig, DMI_SBCS_SBACCESS128);
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if (sbaccess128) {
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LOG_INFO("System Bus Access Test 5: SBCS Alignment error test PASSED, all alignments supported");
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LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED, all sbaccess sizes supported.");
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} else {
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 4);
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dmi_write(target, DMI_SBCS, sbcs);
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write_memory_sba_simple(target, legal_address, 0xdeadbeef, sbcs_orig);
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write_memory_sba_simple(target, legal_address, test_patterns, 1, sbcs_orig);
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dmi_read(target, &rd_val, DMI_SBCS);
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LOG_INFO("SBCS.SBACCESS128 = %x",sbaccess128);
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LOG_INFO("SBCS.SBERROR = %x",get_field(rd_val,DMI_SBCS_SBERROR));
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if (get_field(rd_val, DMI_SBCS_SBERROR) == 3) {
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LOG_INFO("System Bus Access Test 5: SBCS Alignment error test PASSED");
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1);
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dmi_write(target, DMI_SBCS, sbcs);
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dmi_read(target, &rd_val, DMI_SBCS);
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if(get_field(rd_val, DMI_SBCS_SBERROR) == 0)
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LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED.");
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else
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LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to clear to 0.");
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} else {
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LOG_ERROR("System Bus Access Test 5: SBCS Alignment error test FAILED");
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LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to set error code.");
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}
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}
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/* Test 6: Set sbbusyerror, only run this case in simulation as it is likely
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// Test 6: Write to misaligned address
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 1);
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dmi_write(target, DMI_SBCS, sbcs);
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dmi_write(target, DMI_SBADDRESS0, legal_address+1);
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if (get_field(rd_val, DMI_SBCS_SBERROR) == 3) {
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1);
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dmi_write(target, DMI_SBCS, sbcs);
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dmi_read(target, &rd_val, DMI_SBCS);
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if(get_field(rd_val, DMI_SBCS_SBERROR) == 0)
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LOG_INFO("System Bus Access Test 6: SBCS address alignment error test PASSED");
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else
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LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to clear to 0.");
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} else {
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LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to set error code.");
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}
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/* Test 7: Set sbbusyerror, only run this case in simulation as it is likely
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* impossible to hit otherwise */
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if (riscv_run_sim_only_tests) {
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if (run_sbbusyerror_test) {
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1);
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dmi_write(target, DMI_SBCS, sbcs);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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for (int i = 0; i < 16; i++) {
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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}
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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for (int i = 0; i < 16; i++) {
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dmi_write(target, DMI_SBADDRESS0, legal_address);
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}
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dmi_read(target, &rd_val, DMI_SBCS);
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if (get_field(rd_val, DMI_SBCS_SBBUSYERROR)) {
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@ -3035,11 +3064,11 @@ static int riscv013_test_sba_config_reg(struct target *target,
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dmi_write(target, DMI_SBCS, sbcs);
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dmi_read(target, &rd_val, DMI_SBCS);
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if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0)
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LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED");
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LOG_INFO("System Bus Access Test 7: SBCS sbbusyerror test PASSED.");
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else
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LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0");
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LOG_ERROR("System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to clear to 0.");
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} else {
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LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set");
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LOG_ERROR("System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to set error code.");
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}
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}
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@ -3047,7 +3076,8 @@ static int riscv013_test_sba_config_reg(struct target *target,
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}
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void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t data, uint32_t sbcs)
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void write_memory_sba_simple(struct target *target, target_addr_t addr,
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uint32_t* write_data, uint32_t write_size, uint32_t sbcs)
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{
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RISCV013_INFO(info);
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@ -3070,14 +3100,19 @@ void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t
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dmi_write(target, DMI_SBADDRESS3, masked_addr);
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}
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dmi_write(target, DMI_SBDATA0, data);
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/* Write SBDATA registers starting with highest address, since write to
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* SBDATA0 triggers write */
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for (int i = write_size-1; i >= 0; i--) {
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dmi_write(target,DMI_SBDATA0+i,write_data[i]);
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}
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}
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uint32_t read_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t sbcs)
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uint32_t* read_memory_sba_simple(struct target *target, target_addr_t addr,
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uint32_t read_size, uint32_t sbcs)
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{
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RISCV013_INFO(info);
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uint32_t rd_val;
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uint32_t* rd_val = malloc(read_size*sizeof(uint32_t));
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uint32_t rd_sbcs;
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uint32_t masked_addr;
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@ -3088,7 +3123,8 @@ uint32_t read_memory_sba_simple(struct target *target, target_addr_t addr, uint3
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uint32_t sbcs_readonaddr = set_field(sbcs, DMI_SBCS_SBREADONADDR, 1);
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dmi_write(target, DMI_SBCS, sbcs_readonaddr);
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for (uint32_t i = 0; i < sba_size/32; i++) {
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// Write addresses starting with highest address register
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for (int i = sba_size/32-1; i >= 0; i--) {
|
||||
masked_addr = (addr >> 32*i) & 0xffffffff;
|
||||
|
||||
if (i != 3)
|
||||
|
|
@ -3099,7 +3135,9 @@ uint32_t read_memory_sba_simple(struct target *target, target_addr_t addr, uint3
|
|||
|
||||
read_sbcs_nonbusy(target, &rd_sbcs);
|
||||
|
||||
dmi_read(target, &rd_val, DMI_SBDATA0);
|
||||
for (uint32_t i = 0; i < read_size; i++) {
|
||||
dmi_read(target, &(rd_val[i]), DMI_SBDATA0+i);
|
||||
}
|
||||
|
||||
return rd_val;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -190,8 +190,6 @@ uint64_t riscv_scratch_ram_address;
|
|||
|
||||
bool riscv_prefer_sba;
|
||||
|
||||
bool riscv_run_sim_only_tests;
|
||||
|
||||
/* In addition to the ones in the standard spec, we'll also expose additional
|
||||
* CSRs in this list.
|
||||
* The list is either NULL, or a series of ranges (inclusive), terminated with
|
||||
|
|
@ -1432,8 +1430,8 @@ COMMAND_HANDLER(riscv_dmi_write)
|
|||
|
||||
COMMAND_HANDLER(riscv_test_sba_config_reg)
|
||||
{
|
||||
if (CMD_ARGC != 3) {
|
||||
LOG_ERROR("Command takes exactly 3 arguments");
|
||||
if (CMD_ARGC != 4) {
|
||||
LOG_ERROR("Command takes exactly 4 arguments");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
|
|
@ -1441,13 +1439,17 @@ COMMAND_HANDLER(riscv_test_sba_config_reg)
|
|||
RISCV_INFO(r);
|
||||
|
||||
target_addr_t legal_address;
|
||||
uint32_t num_words;
|
||||
target_addr_t illegal_address;
|
||||
bool run_sbbusyerror_test;
|
||||
COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], legal_address);
|
||||
COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1], illegal_address);
|
||||
COMMAND_PARSE_ON_OFF(CMD_ARGV[2], riscv_run_sim_only_tests);
|
||||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], num_words);
|
||||
COMMAND_PARSE_NUMBER(u64, CMD_ARGV[2], illegal_address);
|
||||
COMMAND_PARSE_ON_OFF(CMD_ARGV[3], run_sbbusyerror_test);
|
||||
|
||||
if (r->test_sba_config_reg) {
|
||||
return r->test_sba_config_reg(target, legal_address, illegal_address);
|
||||
return r->test_sba_config_reg(target, legal_address, num_words,
|
||||
illegal_address, run_sbbusyerror_test);
|
||||
} else {
|
||||
LOG_ERROR("test_sba_config_reg is not implemented for this target.");
|
||||
return ERROR_FAIL;
|
||||
|
|
@ -1525,12 +1527,14 @@ static const struct command_registration riscv_exec_command_handlers[] = {
|
|||
.name = "test_sba_config_reg",
|
||||
.handler = riscv_test_sba_config_reg,
|
||||
.mode = COMMAND_ANY,
|
||||
.usage = "riscv test_sba_config_reg legal_address"
|
||||
"illegal_address riscv_run_sim_only_tests[on/off]",
|
||||
.usage = "riscv test_sba_config_reg legal_address num_words"
|
||||
"illegal_address run_sbbusyerror_test[on/off]",
|
||||
.help = "Perform a series of tests on the SBCS register."
|
||||
"Inputs are a legal address for read/write tests,"
|
||||
"an illegal address for error flag/handling cases, and"
|
||||
"whether sim_only tests should be run."
|
||||
"Inputs are a legal, 128-byte aligned address and a number of words to"
|
||||
"read/write starting at that address (i.e., address range [legal address,"
|
||||
"legal_address+word_size*num_words) must be legally readaable/writable)"
|
||||
", an illegal, 128-byte aligned address for error flag/handling cases,"
|
||||
"and whether sbbusyerror test should be run."
|
||||
},
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
|
|
|||
|
|
@ -118,7 +118,7 @@ typedef struct {
|
|||
int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
|
||||
|
||||
int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address,
|
||||
target_addr_t illegal_address);
|
||||
uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
|
||||
|
||||
} riscv_info_t;
|
||||
|
||||
|
|
@ -133,7 +133,7 @@ extern uint64_t riscv_scratch_ram_address;
|
|||
|
||||
extern bool riscv_prefer_sba;
|
||||
|
||||
extern bool riscv_run_sim_only_tests;
|
||||
extern bool riscv_run_sbbusyerror_test;
|
||||
|
||||
/* Everything needs the RISC-V specific info structure, so here's a nice macro
|
||||
* that provides that. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue