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riscv-openocd
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Fix some build issues

This commit is contained in:
Ryan Macdonald 2018-04-09 11:38:41 -07:00
parent 99f2f5a272
commit c2c52c89b1
3 changed files with 7 additions and 7 deletions
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6
src/target/riscv/riscv-013.c
View File

@ -2908,7 +2908,7 @@ static int riscv013_test_sba_config_reg(struct target *target,
prev_addr = curr_addr;
read_sbcs_nonbusy(target, &sbcs);
dmi_read(target, &curr_addr, DMI_SBADDRESS0);
if ((curr_addr - prev_addr != (1 << sbaccess)) && i != 0) {
if ((curr_addr - prev_addr != (1 << (uint32_t)sbaccess)) && i != 0) {
LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x", sbaccess);
test_passed = false;
}
@ -2928,7 +2928,7 @@ static int riscv013_test_sba_config_reg(struct target *target,
prev_addr = curr_addr;
read_sbcs_nonbusy(target, &sbcs);
dmi_read(target, &curr_addr, DMI_SBADDRESS0);
if ((curr_addr - prev_addr != (1 << sbaccess)) && i != 0) {
if ((curr_addr - prev_addr != (1 << (uint32_t)sbaccess)) && i != 0) {
LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x", sbaccess);
test_passed = false;
}
@ -2991,7 +2991,7 @@ static int riscv013_test_sba_config_reg(struct target *target,
/* Test 6: Set sbbusyerror, only run this case in simulation as it is likely
* impossible to hit otherwise */
if (run_sim_only_tests) {
if (riscv_run_sim_only_tests) {
sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1);
dmi_write(target, DMI_SBCS, sbcs);

6
src/target/riscv/riscv.c
View File

@ -190,7 +190,7 @@ uint64_t riscv_scratch_ram_address;
bool riscv_prefer_sba;
bool run_sim_only_tests;
bool riscv_run_sim_only_tests;
/* In addition to the ones in the standard spec, we'll also expose additional
* CSRs in this list.
@ -1444,7 +1444,7 @@ COMMAND_HANDLER(riscv_test_sba_config_reg)
target_addr_t illegal_address;
COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], legal_address);
COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1], illegal_address);
COMMAND_PARSE_ON_OFF(CMD_ARGV[2], run_sim_only_tests);
COMMAND_PARSE_ON_OFF(CMD_ARGV[2], riscv_run_sim_only_tests);
if (r->test_sba_config_reg) {
return r->test_sba_config_reg(target, legal_address, illegal_address);
@ -1526,7 +1526,7 @@ static const struct command_registration riscv_exec_command_handlers[] = {
.handler = riscv_test_sba_config_reg,
.mode = COMMAND_ANY,
.usage = "riscv test_sba_config_reg legal_address"
"illegal_address run_sim_only_tests[on/off]",
"illegal_address riscv_run_sim_only_tests[on/off]",
.help = "Perform a series of tests on the SBCS register."
"Inputs are a legal address for read/write tests,"
"an illegal address for error flag/handling cases, and"

2
src/target/riscv/riscv.h
View File

@ -133,7 +133,7 @@ extern uint64_t riscv_scratch_ram_address;
extern bool riscv_prefer_sba;
extern bool run_sim_only_tests;
extern bool riscv_run_sim_only_tests;
/* Everything needs the RISC-V specific info structure, so here's a nice macro
* that provides that. */