clairexen
22765ef0a5
Merge pull request #2339 from zachjs/display-format-0s
...
Allow %0s $display format specifier
2020-08-18 17:39:01 +02:00
clairexen
4aa0dc4dc7
Merge pull request #2338 from zachjs/const-branch-finish
...
Propagate const_fold through generate blocks and branches
2020-08-18 17:38:07 +02:00
clairexen
a9681f4e06
Merge pull request #2317 from zachjs/expand-genblock
...
Fix generate scoping issues
2020-08-18 17:37:11 +02:00
Claire Wolf
7f767bf2b7
Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-08-18 17:29:49 +02:00
clairexen
5ee9349647
Merge pull request #2281 from zachjs/const-real
...
Allow reals as constant function parameters
2020-08-18 17:22:20 +02:00
Zachary Snow
2ee0b8ebea
Propagate const_fold through generate blocks and branches
2020-08-09 17:21:08 -04:00
Zachary Snow
96ec9acf84
Allow %0s $display format specifier
2020-08-09 17:19:49 -04:00
Lukasz Dalek
ba08c25133
Fix subarray access condition
...
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 16:16:04 +02:00
Lukasz Dalek
83ddc62034
Rewrite multirange arrays sizes [n] as [n-1:0]
...
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 14:48:27 +02:00
Zachary Snow
c3e95eb1ab
Fix generate scoping issues
...
- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214 , resolves #1456
2020-07-31 20:32:47 -06:00
Miodrag Milanovic
cc02d58194
Clear last error message
2020-07-29 15:28:33 +02:00
clairexen
45e96d5d87
Merge pull request #2301 from zachjs/for-loop-errors
...
Clearer for loop error messages
2020-07-28 14:07:26 +02:00
Zachary Snow
58da181af9
Clearer for loop error messages
2020-07-25 10:37:16 -06:00
Zachary Snow
f69daf4830
Allow blocks with declarations within constant functions
2020-07-25 10:16:12 -06:00
Zachary Snow
59c4ad8ed3
Avoid generating wires for function args which are constant
2020-07-24 21:18:24 -06:00
Zachary Snow
f285f7b769
Allow reals as constant function parameters
2020-07-19 20:27:09 -06:00
Claire Wolf
51ee0b683f
Treat all bison warnings as errors in verilog front-end
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:57:31 +02:00
Claire Wolf
7a79843cc3
Use %precedence in verilog_parser.y
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:54:28 +02:00
Claire Wolf
24540291c7
Fix bison warnings for missing %empty
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:50:59 +02:00
Claire Wolf
1f4e452609
Run bison with -Wall for verilog front-end
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:49:36 +02:00
clairexen
021ce8e596
Merge pull request #2257 from antmicro/fix-conflicts
...
Restore #2203 and #2244 and fix parser conflicts
2020-07-15 11:49:09 +02:00
Kamil Rakoczy
02c071888b
Add missing semicolons
...
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-15 10:15:13 +02:00
Claire Wolf
f9ed09423e
Add AST_EDGE support to AstNode::detect_latch(), fixes #2241
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-10 18:41:13 +02:00
Kamil Rakoczy
d77b3305d8
Fix S/R conflicts
...
This commit fixes S/R conflicts introduced by commit 6f9be93
.
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-10 15:03:53 +02:00
Kamil Rakoczy
0ffaddee5e
Fix R/R conflicts
...
This commit fixes R/R conflicts introduced by commit 7e83a51
.
Parameter logic is already defined as part of `param_range_type` rule.
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-10 15:03:01 +02:00
Kamil Rakoczy
de649b9194
Revert "Revert PRs #2203 and #2244."
...
This reverts commit 9c120b89ac
.
2020-07-10 09:59:48 +02:00
whitequark
dc35ef05f9
verilog_parser: turn S/R and R/R conflicts into hard errors.
...
Fixes #2253 .
2020-07-09 19:36:59 +00:00
whitequark
9c120b89ac
Revert PRs #2203 and #2244 .
...
This reverts commit 7e83a51fc9
.
This reverts commit b422f2e4d0
.
This reverts commit 7cb56f34b0
.
This reverts commit 6f9be939bd
.
This reverts commit 76a34dc5f3
.
2020-07-09 19:36:32 +00:00
Lukasz Dalek
7e83a51fc9
Support logic typed parameters
...
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-07-06 09:18:48 +02:00
clairexen
3d8d98d709
Merge pull request #2132 from YosysHQ/eddie/verific_initial
...
verific: rewrite initial assume/asserts prior to elaboration
2020-07-02 17:50:22 +02:00
clairexen
7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar
...
Signed and macro grammar update
2020-07-01 16:41:32 +02:00
clairexen
8ce4f8790e
Merge pull request #2179 from splhack/static-cast
...
Support SystemVerilog Static Cast
2020-07-01 16:40:20 +02:00
clairexen
9d658a1970
Merge pull request #2136 from zachjs/master
...
Allow constant function calls in for loops and generate if and case
2020-06-30 17:38:49 +02:00
Miodrag Milanovic
561890c4e8
Update verific API version check
2020-06-30 12:13:13 +02:00
Zachary Snow
27cec16cda
Allow constant function calls in for loops and generate if and case
2020-06-29 16:06:17 -06:00
Miodrag Milanovic
b822beb1b2
Fix crash in verific frontend
2020-06-26 20:11:01 +02:00
Lukasz Dalek
6f9be939bd
Parse macro call attached semicolon as empty expression
...
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-26 15:38:20 +02:00
Lukasz Dalek
7cb56f34b0
Fix integer signing grammar
...
This commit fixes signed/unsigned grammar in parameters as defined in SV
LRM A2.2.1. Example of correct parameters:
parameter integer signed i = 0;
parameter integer unsigned i = 0;
Example of incorrect parameters:
parameter signed integer i = 0;
parameter unsigned integer i = 0;
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-26 15:35:56 +02:00
whitequark
12c016ebdc
Merge pull request #2188 from antmicro/missing-operators
...
Add logic-assignments operators
2020-06-26 07:30:27 +00:00
whitequark
d6bdc09422
Merge pull request #2189 from antmicro/optional-labels
...
Add support for optional labels
2020-06-26 07:29:24 +00:00
clairexen
c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs
...
Use (and ignore) the expression provided to log_assert in NDEBUG builds
2020-06-25 18:21:51 +02:00
Kamil Rakoczy
539087f417
Support missing sub-assign and and-assign operators
...
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-25 13:29:06 +02:00
Miodrag Milanovic
4aec50a863
optimization, all items should have same attributes
2020-06-25 09:18:53 +02:00
Lukasz Dalek
a4b4c22c96
Support missing xor-assign operator
...
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 14:32:12 +02:00
Lukasz Dalek
a8750b496e
Support optional labels at the end of package definition
...
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 11:57:45 +02:00
Lukasz Dalek
3b81a1b809
Support optional labels at the end of module definition
...
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 11:57:45 +02:00
Kamil Rakoczy
22408f24c7
Add plus-assignment operator
...
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:54:30 +02:00
Kamil Rakoczy
416a66aee8
Add or-assignment operator
...
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:53:50 +02:00
Miodrag Milanovic
f993d18755
verific - import attributes for net buses as well
2020-06-24 11:01:06 +02:00
Kazuki Sakamoto
429d37ff41
static cast: simplify
2020-06-19 19:09:43 -07:00
Kazuki Sakamoto
185bbbe681
static cast: support changing size and signedness
...
Support SystemVerilog Static Cast
- size
- signedness
- (type is not supposted yet)
Fix #535
2020-06-19 17:39:20 -07:00
whitequark
118e4caa37
Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().
2020-06-19 15:48:58 +00:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Anonymous Maarten
504f220619
MSVC does not understand __builtin_unreachable
2020-06-17 15:10:08 +02:00
Anonymous Maarten
35008e6d40
MSVC cannot omit operand in conditional
2020-06-17 15:10:08 +02:00
clairexen
b2a0f49371
Merge pull request #2131 from YosysHQ/claire/preserveffs
...
Do not optimize away FFs in "prep" and Verific front-end
2020-06-10 12:44:23 +02:00
Miodrag Milanovic
d6bec3ba1c
verific - detect missing memory to prevent crash.
2020-06-10 11:27:44 +02:00
clairexen
5c426d2bff
Merge pull request #2112 from YosysHQ/claire/fix2040
...
Add latch detection for use_case_method in part-select write
2020-06-09 18:27:59 +02:00
Claire Wolf
3c7122c378
Do not optimize away FFs in "prep" and Verific fron-end
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 15:54:14 +02:00
Peter Crozier
f80b09fc58
Support 2D packed bit arrays in struct/union.
2020-06-09 13:52:09 +01:00
Peter Crozier
01ec681373
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 20:34:52 +01:00
Peter Crozier
76c499db71
Support packed arrays in struct/union.
2020-06-07 18:33:11 +01:00
Claire Wolf
7ad0c49905
Add latch detection for use_case_method in part-select write, fixes #2040
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 23:25:59 +02:00
clairexen
352731df4e
Merge pull request #2041 from PeterCrozier/struct
...
Implementation of SV structs.
2020-06-04 18:26:07 +02:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
...
abc9: -dff improvements
2020-06-04 08:15:25 -07:00
whitequark
3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
...
Preserve 'signed'-ness of a verilog wire through RTLIL
2020-06-04 11:23:06 +00:00
Peter Crozier
0d3f7ea011
Merge branch 'master' into struct
2020-06-03 17:19:28 +01:00
Miodrag Milanovic
71072d1945
Support asymmetric memories for verific frontend
2020-06-01 10:30:03 +02:00
clairexen
0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic
...
ast/simplify: don't bitblast async ROMs declared as `logic`
2020-05-29 16:52:11 +02:00
whitequark
626c74adbd
Merge pull request #2097 from whitequark/ilang_lexer-fix-erange
...
ilang_lexer: fix check for out of range literal
2020-05-29 09:04:27 +00:00
whitequark
13b2963ded
ilang_lexer: fix check for out of range literal.
...
Commit ca70a104
did not use a correct check.
2020-05-29 06:58:44 +00:00
whitequark
2116d9500c
Merge pull request #2033 from boqwxp/cleanup-verilog-lexer
...
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
2020-05-29 06:46:33 +00:00
Rupert Swarbrick
6aa0f72ae9
Silence spurious warning in Verilog lexer when compiling with GCC
...
The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.
2020-05-26 17:54:57 +01:00
Eddie Hung
1ebf7155a7
aiger: cleanup
2020-05-25 08:43:33 -07:00
Eddie Hung
c5a9abba11
verilog: move attr from simple_behav_stmt to its children to attach
2020-05-25 07:36:53 -07:00
Eddie Hung
1c117ac023
verilog: do not warn for attributes on null statements
2020-05-25 07:36:53 -07:00
Eddie Hung
88bddb37c9
verilog: handle empty generate statement by removing gen_stmt_or_null...
...
... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.
2020-05-25 07:36:53 -07:00
Eddie Hung
d21a07c7b5
verilog: fix #2037 by permitting (and freeing) attributes on null stmt
2020-05-25 07:36:53 -07:00
Eddie Hung
574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
...
verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
2020-05-21 11:00:36 -07:00
Eddie Hung
38e858af8d
Update frontends/verilog/verilog_parser.y
...
Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-05-21 09:10:56 -07:00
Marcelina Kościelnicka
aee439360b
Add force_downto and force_upto wire attributes.
...
Fixes #2058 .
2020-05-19 01:42:40 +02:00
Eddie Hung
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
...
abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
Claire Wolf
fa8cb3e35d
Revert "Add support for non-power-of-two mem chunks in verific importer"
...
This reverts commit 173aa27ca5
.
2020-05-17 11:31:11 +02:00
Eddie Hung
39fa1e160d
verific: rewrite initial assume/asserts prior to elaboration
2020-05-15 14:05:28 -07:00
Eddie Hung
7101ef550b
verilog: attributes before task enable (but 13 s/r conflicts)
2020-05-14 16:10:11 -07:00
Eddie Hung
4017cc6380
aiger: -xaiger to return $_FF_ flops
2020-05-14 10:33:56 -07:00
Eddie Hung
6f4f795953
aiger/xaiger: use odd for negedge clk, even for posedge
...
Since abc9 doesn't like negative mergeability values
2020-05-14 10:33:56 -07:00
Eddie Hung
483a190c1b
aiger: -xaiger to parse initial state back into (* init *) on Q wire
2020-05-14 10:33:56 -07:00
Eddie Hung
53fc3ed645
aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created
...
according to mergeability class, and init state as cell attr
2020-05-14 10:33:56 -07:00
Eddie Hung
5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042
...
verilog: error if no direction given for task arguments, default to input in SV mode
2020-05-14 09:45:54 -07:00
Claire Wolf
f02e20907e
Merge pull request #2052 from YosysHQ/claire/verific_memfix
...
Add support for non-power-of-two mem chunks in verific importer
2020-05-14 18:45:13 +02:00
Claire Wolf
ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
...
ast: swap range regardless of range_left >= 0
2020-05-14 18:06:18 +02:00
Claire Wolf
173aa27ca5
Add support for non-power-of-two mem chunks in verific importer
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-14 14:38:13 +02:00
Eddie Hung
237962debd
verilog: default to input in sv mode if task/func has no dir ...
...
otherwise error
2020-05-13 13:33:37 -07:00
Peter Crozier
17f050d3c6
Allow structs within structs.
2020-05-12 17:20:34 +01:00
Peter Crozier
f482c9c016
Generalise structs and add support for packed unions.
2020-05-12 14:25:33 +01:00
Eddie Hung
1f3003be7d
verilog: error out when non-ANSI task/func arguments
2020-05-11 13:00:36 -07:00
Peter Crozier
0b6b47ca67
Implement SV structs.
2020-05-08 14:40:49 +01:00
whitequark
ebfdf61eb9
Merge pull request #2022 from Xiretza/fallthroughs
...
Avoid switch fall-through warnings
2020-05-08 05:30:32 +00:00
Claire Wolf
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
...
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
Xiretza
695150b037
Add YS_FALLTHROUGH macro to mark case fall-through
...
C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
2020-05-07 13:39:34 +02:00
Eddie Hung
a299e606f8
Merge pull request #2028 from zachjs/master
...
verilog: allow null gen-if then block
2020-05-06 12:10:28 -07:00
Zachary Snow
8f9bba1bbf
verilog: allow null gen-if then block
2020-05-06 08:43:02 -04:00
Alberto Gonzalez
323aa1df75
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
2020-05-06 07:22:17 +00:00
Eddie Hung
283b1130a6
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup
...
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-05 07:59:40 -07:00
Eddie Hung
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
...
verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
whitequark
66d0ed2bcc
ast/simplify: don't bitblast async ROMs declared as `logic`.
...
Fixes #2020 .
2020-05-05 04:16:59 +00:00
Eddie Hung
e936ac61ea
ast: swap range regardless of range_left >= 0
2020-05-04 12:18:20 -07:00
Eddie Hung
eb5eb60fd4
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
Eddie Hung
22bf22fab4
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
Eddie Hung
eca9fc01a7
verilog: set src attribute for primitives
2020-05-04 10:22:05 -07:00
Eddie Hung
584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations
...
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-04 08:58:50 -07:00
Eddie Hung
a0afa1787e
aiger: fixes for ports that have start_offset != 0
2020-05-02 10:00:32 -07:00
Claire Wolf
88185f8959
Fix handling of signed indices in bit slices
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Claire Wolf
589ed2d970
Add AST_SELFSZ and improve handling of bit slices
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Claire Wolf
bbbce0d1c5
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
whitequark
bbde241942
Merge pull request #2001 from whitequark/wasi
...
Add WASI platform support
2020-05-01 21:28:20 +00:00
Claire Wolf
d047ca8b11
Merge pull request #1981 from YosysHQ/claire/fix1837
...
Clear current_scope when done with RTLIL generation
2020-05-01 14:58:41 +02:00
Alberto Gonzalez
b0268b1311
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-01 07:17:27 +00:00
whitequark
b43c282e4e
Add WASI platform support.
...
This includes the following significant changes:
* Patching ezsat and minisat to disable resource limiting code
on WASM/WASI, since the POSIX functions they use are unavailable.
* Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
does not support spawning subprocesses (i.e. Emscripten or WASI).
This definition hides the definition of `run_command()`.
* Adding a new Makefile flag, DISABLE_SPAWN, present in the same
condition. This flag disables all passes that require spawning
subprocesses for their function.
2020-04-30 18:56:25 +00:00
Eddie Hung
5017ff4a97
verific: ignore anonymous enums
2020-04-30 07:48:47 -07:00
Eddie Hung
97bfe65d3a
verific: support VHDL enums too
2020-04-27 15:17:13 -07:00
Vamsi K Vytla
adb483ddfd
frontends/json/jsonparse.cc: Like the upto field read_json can also read the signedness of a wire
2020-04-27 10:36:18 -07:00
Vamsi K Vytla
5f9cd2e2f6
Preserve 'signed'-ness of a verilog wire through RTLIL
...
As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987 , now:
RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
2020-04-27 09:44:24 -07:00
Eddie Hung
dd5f206d9e
verific: recover wiretype/enum attr as part of import_attributes()
2020-04-27 08:43:54 -07:00
Eddie Hung
b52eccef3a
Revert "verific: import enum attributes from verific"
...
This reverts commit 5028e17f7d
.
2020-04-24 11:57:55 -07:00
Eddie Hung
d3555c667c
verific: do not assert if wire not found; warn instead
2020-04-23 16:28:11 -07:00
Eddie Hung
5028e17f7d
verific: import enum attributes from verific
2020-04-22 17:26:56 -07:00
Claire Wolf
9f1fb11b1d
Clear current_scope when done with RTLIL generation, fixes #1837
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-22 14:51:20 +02:00
Marcelina Kościelnicka
06a344efcb
ilang, ast: Store parameter order and default value information.
...
Fixes #1819 , #1820 .
2020-04-21 19:09:00 +02:00
Claire Wolf
9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite
...
Improved rewrite code for writing to bit slice
2020-04-21 18:46:52 +02:00
whitequark
abc8f1fcb6
Merge pull request #1961 from whitequark/paramod-original-name
...
ast, rpc: record original name of $paramod\* as \hdlname attribute
2020-04-21 01:43:20 +00:00
Claire Wolf
35990b95ec
Extend support for format strings in Verilog front-end
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-18 14:08:51 +02:00
whitequark
41421f5dca
ast, rpc: record original name of $paramod\* as \hdlname attribute.
...
The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.
This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
2020-04-18 03:47:28 +00:00
Alberto Gonzalez
00d74f0b9c
Set Verilog source location for explicit blocks (`begin` ... `end`).
2020-04-17 06:23:03 +00:00
Alberto Gonzalez
10a814f978
Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.
2020-04-17 06:16:59 +00:00
Alberto Gonzalez
9253497358
Add location information to `AST_CONSTANT` nodes.
2020-04-16 19:11:47 +00:00
Claire Wolf
e86ba3b94d
Make mask-and-shift the default for bitselwrite
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:52 +02:00
Claire Wolf
e1fb12a4b9
Add LookaheadRewriter for proper bitselwrite support
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:07 +02:00
David Shah
4d02505820
ast: Fix handling of identifiers in the global scope
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 10:30:07 +01:00
Claire Wolf
4711fea6c0
Improved rewrite code for writing to bit slice (disabled for now)
...
This adds the new rewrite rule. But it's still missing a check that makes
sure the new rewrite rule is actually a valid substitute in the always
block being processed. Therefore the new rewrite rule is just disabled
for now.
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-15 17:44:37 +02:00
whitequark
2d436bc4f1
Merge pull request #1918 from whitequark/simplify-improve_enum
...
ast/simplify: improve enum handling
2020-04-15 14:16:50 +00:00
whitequark
2106f78bb1
ast/simplify: improve enum handling.
...
Before this commit, enum values were serialized as attributes of form
\enum_<width>_<value>
where <value> was a decimal signed integer.
This has multiple drawbacks:
* Enums with large values would be hard to process for downstream
tooling that cannot parse arbitrary precision decimals. (In fact
Yosys also did not correctly process enums with large values,
and would overflow `int`.)
* Enum value attributes were not confined to their own namespace,
making it harder for downstream tooling to enumerate all such
attributes, as opposed to looking up any specific value.
* Enum values could not include x or z, which are explicitly
permitted in the SystemVerilog standard.
After this commit, enum values are serialized as attributes of form
\enum_value_<value>
where <value> is a bit sequence of the appropriate width.
2020-04-15 14:14:50 +00:00
Claire Wolf
9b4dab397e
Fix 5bba9c3
, closes #1876
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-14 21:05:07 +02:00
whitequark
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl
...
support using previously declared types/localparams/parameters in package
2020-04-14 12:40:00 +00:00
whitequark
0e1beb6f30
Merge pull request #1880 from jjj11x/duplicate_enum
...
duplicated enum item names should result in an error
2020-04-14 12:39:28 +00:00
whitequark
5448f9c85d
Merge pull request #1910 from boqwxp/cleanup_ilang_parser
...
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 08:40:45 +00:00
Alberto Gonzalez
8a84674a42
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 04:22:00 +00:00
David Shah
0a178de1b3
verilog: Fix write to deleted object
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-12 18:49:09 +01:00
whitequark
f1d9ca1563
Merge pull request #1875 from whitequark/read_ilang-int_overflow
...
Improve handling of integer literals in RTLIL frontend
2020-04-09 04:02:57 +00:00
Henner Zeller
c15040c218
aigerparse: only define __STDC_FORMAT_MACROS it not already before.
2020-04-07 12:50:31 -07:00
Jeff Wang
dbfd6b7530
duplicated enum item names should result in an error
2020-04-07 02:30:11 -04:00
Jeff Wang
249876b614
support using previously declared types/localparams/params in package
...
(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
whitequark
b494d4c656
read_ilang: improve style. NFC.
...
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-04-06 18:31:15 +00:00
whitequark
d22888ce74
read_ilang: improve error message for overly long wires.
...
Fixes #1838 .
2020-04-06 10:33:02 +00:00
whitequark
ca70a1049f
read_ilang: detect overflow of integer literals.
2020-04-06 10:32:02 +00:00
Eddie Hung
cf716e1fff
Merge pull request #1853 from YosysHQ/eddie/fix_dynslice
...
ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-02 12:27:10 -07:00
Eddie Hung
5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings
...
IdString: use more ID::*, make them easier to use, speed up IdString::in()
2020-04-02 11:47:25 -07:00
Eddie Hung
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
Claire Wolf
c69f4b246a
Merge pull request #1846 from dh73/ast_fe
...
Adding error message for when size (width) of number literal is zero
2020-04-02 18:15:15 +02:00
Eddie Hung
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
Eddie Hung
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
...
kernel: speedup by using more pass-by-const-ref
2020-04-02 07:13:33 -07:00
David Shah
f3405e7c79
Merge pull request #1844 from YosysHQ/dave/gen-source-loc
...
verilog: Add location info for generate constructs
2020-04-01 20:55:24 +01:00
David Shah
c3997c77a5
verilog: Add location info for generate constructs
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-01 18:47:20 +01:00
Eddie Hung
c22fb76664
ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-01 09:59:23 -07:00
Claire Wolf
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
...
ast: simplify to fully populate dynamic slicing case transformation
2020-04-01 08:38:14 +02:00
Eddie Hung
5132f4099b
ast: simplify to fully populate dynamic slicing case transformation
2020-03-31 11:52:14 -07:00
Diego H
c859bcf71b
Replacing log_error for log_file_error due consistency
2020-03-31 12:01:29 -06:00
Diego H
92809bb1d3
Adding error message for when size (width) of number literal is zero
2020-03-30 17:18:13 -06:00
Eddie Hung
05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup
...
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-30 13:06:10 -07:00
Alberto Gonzalez
b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to `fixup_ports()`.
...
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 18:14:32 +00:00
N. Engelhardt
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope
...
Support module/package/interface/block scope for typedef names.
2020-03-30 13:55:39 +02:00
N. Engelhardt
2c847e7efe
Merge pull request #1778 from rswarbrick/sv-defines
...
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-30 13:51:12 +02:00
Claire Wolf
1bf2bdf05b
Merge pull request #1607 from whitequark/simplify-simplify-meminit
...
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
2020-03-27 17:28:26 +01:00
Peter Crozier
f8c065ed1c
Inline productions to follow house style.
2020-03-27 16:21:45 +00:00
Rupert Swarbrick
044ca9dde4
Add support for SystemVerilog-style `define to Verilog frontend
...
This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
Alberto Gonzalez
6040593994
Revert over-aggressive change to a more modest cleanup.
2020-03-27 09:46:40 +00:00
Peter Crozier
9a8a644ad1
Error duplicate declarations of a typedef name in the same scope.
2020-03-24 14:35:21 +00:00
Peter Crozier
ecc22f7fed
Support module/package/interface/block scope for typedef names.
2020-03-23 20:07:22 +00:00
Peter Crozier
6cad865d12
Simplify was not being called for packages. Broke typedef enums.
2020-03-22 18:20:46 -07:00
Peter Crozier
c06eda2504
Build pkg_user_types before parsing in case of changes in the design.
2020-03-22 18:20:46 -07:00
Peter
0aaa36ca6d
Clear pkg_user_types if no packages following a 'design -reset-vlog'.
2020-03-22 18:20:46 -07:00
Peter
14f32028ec
Parser changes to support typedef.
2020-03-22 18:20:46 -07:00
Eddie Hung
f828cb5132
Merge pull request #1788 from YosysHQ/eddie/fix_ndebug
...
Fix NDEBUG warnings
2020-03-19 14:58:06 -07:00
Miodrag Milanović
d46259becd
Merge pull request #1787 from YosysHQ/mmicko/lexer_deps
...
Add dependency to verilog_lexer.cc
2020-03-19 18:24:40 +01:00
Miodrag Milanovic
dc75ed7dac
Add one mode dependency
2020-03-19 16:53:40 +01:00
Eddie Hung
43092f063f
Fix NDEBUG warnings
2020-03-19 08:48:39 -07:00
N. Engelhardt
b473264a06
Merge pull request #1775 from huaixv/asserts_locations
...
Add precise locations for asserts
2020-03-19 13:12:18 +01:00
Alberto Gonzalez
eb30d66d01
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-19 07:29:00 +00:00
huaixv
cd82ccd258
Add precise locations for asserts
2020-03-19 10:22:07 +08:00
Eddie Hung
4555b5b819
kernel: more pass by const ref, more speedups
2020-03-18 11:21:53 -07:00
Alberto Gonzalez
6dd2024965
Add AST node source location information in a couple more parser rules.
2020-03-17 06:22:12 +00:00
Miodrag Milanović
569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux
...
refixed parsing of constant with comment between size and value
2020-03-14 13:34:59 +02:00
Miodrag Milanović
faf4ee69de
Merge pull request #1754 from boqwxp/precise_locations
...
Set AST node source location in more parser rules.
2020-03-14 11:18:39 +02:00
Marcus Comstedt
5e94bf0291
refixed parsing of constant with comment between size and value
...
The three parts of a based constant (size, base, digits) are now three
separate tokens, allowing the linear whitespace (including comments)
between them to be treated as normal inter-token whitespace.
2020-03-11 18:21:44 +01:00
jiegec
7b679eecb3
Fix compilation for emcc
2020-03-11 22:09:24 +08:00
Eddie Hung
2d63bf5877
verilog: also set location for simple_behavioral_stmt
2020-03-10 10:29:24 -07:00
Alberto Gonzalez
da8270aa01
Set AST source locations in more parser rules.
2020-03-10 01:50:39 +00:00
Claire Wolf
a7cc4673c3
Fix partsel expr bit width handling and add test case
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-08 16:12:12 +01:00
Claire Wolf
d59da5a4e4
Fix bison warning for "pure-parser" option
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-03 08:41:55 -08:00