Eddie Hung
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f8f0ffe786
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Small opt
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2019-07-10 18:56:50 -07:00 |
Eddie Hung
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4a995c5d80
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Change how to specify flops to ABC again
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2019-07-10 17:54:56 -07:00 |
Eddie Hung
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a092c48f03
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Use split_tokens()
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2019-07-10 17:34:51 -07:00 |
Eddie Hung
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a31e17182d
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Refactor and cope with new abc_flop format
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2019-07-01 11:50:34 -07:00 |
Eddie Hung
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ac5f3d500d
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Fix spacing
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2019-07-01 11:10:44 -07:00 |
Eddie Hung
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699d8e3939
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-07-01 10:44:42 -07:00 |
Eddie Hung
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b3f162e94e
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Replace log_assert() with meaningful log_error()
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2019-06-28 12:54:44 -07:00 |
Eddie Hung
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9398921af1
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Refactor for one "abc_carry" attribute on module
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2019-06-27 16:07:14 -07:00 |
Eddie Hung
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469f98b6bd
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Remove unneeded include
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2019-06-27 11:20:40 -07:00 |
Eddie Hung
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f2ead4334a
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Reduce log_debug spam in parse_xaiger()
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2019-06-21 17:33:49 -07:00 |
Eddie Hung
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b75863ca3f
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Workaround issues exposed by gcc-4.8
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2019-06-21 14:31:09 -07:00 |
Eddie Hung
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9faeba7a66
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Fix broken abc9.v test due to inout being 1'bx
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2019-06-20 19:41:27 -07:00 |
Eddie Hung
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014606affe
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Fix issue with part of PI being 1'bx
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2019-06-20 17:38:16 -07:00 |
Eddie Hung
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0c59bc0b75
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Cleanup
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2019-06-16 10:42:00 -07:00 |
Eddie Hung
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fb90d8c18c
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Cleanup
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2019-06-16 09:34:26 -07:00 |
Eddie Hung
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3d1185b835
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Read init from outputs
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2019-06-15 22:41:42 -07:00 |
Eddie Hung
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c04921c3a8
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Fix debug message
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2019-06-15 18:13:44 -07:00 |
Eddie Hung
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b706ae82de
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Fix log_debug messages
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2019-06-15 12:42:18 -07:00 |
Eddie Hung
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7a3c403ba0
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Missing close bracket
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2019-06-15 09:10:01 -07:00 |
Eddie Hung
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2ef2aa997c
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read_aiger to not require clk_name for latches, plus debug
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2019-06-15 09:07:53 -07:00 |
Eddie Hung
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7876b5b8be
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Cover __APPLE__ too for little to big endian
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2019-06-14 12:40:51 -07:00 |
Eddie Hung
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a48b5bfaa5
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Further cleanup based on @daveshah1
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2019-06-14 12:25:06 -07:00 |
Eddie Hung
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97d2656375
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Resolve comments from @daveshah1
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2019-06-14 12:00:02 -07:00 |
Eddie Hung
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a3be25ab0d
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Cleanup
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2019-06-14 10:27:30 -07:00 |
Eddie Hung
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d005568f2e
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Add TODO to parse_xaiger
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2019-06-14 10:11:13 -07:00 |
Eddie Hung
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bc22e2e3ee
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Optimise some more
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2019-06-13 17:02:58 -07:00 |
Eddie Hung
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d09d4e0706
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Move ConstEvalAig to aigerparse.cc
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2019-06-13 16:28:11 -07:00 |
Eddie Hung
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d39a5a77a9
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Add ConstEvalAig specialised for AIGs
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2019-06-13 13:13:48 -07:00 |
Eddie Hung
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342fc0a600
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parse_xaiger to cope with inouts
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2019-06-12 15:45:46 -07:00 |
Eddie Hung
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b21d29598a
|
Consistency
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2019-06-12 09:40:51 -07:00 |
Eddie Hung
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f7a9769c14
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Merge remote-tracking branch 'origin/master' into xaig
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2019-06-12 08:50:39 -07:00 |
Eddie Hung
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2b350401c4
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Fix spacing from spaces to tabs
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2019-06-07 15:44:57 -07:00 |
Eddie Hung
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6934f4bdd5
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Fix spacing (entire file is wrong anyway, will fix later)
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2019-06-07 11:30:36 -07:00 |
Eddie Hung
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d00ae1d6a8
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Remove unnecessary std::getline() for ASCII
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2019-06-07 11:28:25 -07:00 |
Eddie Hung
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a04521c6b7
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Fix read_aiger -- create zero driver, fix init width, parse 'b'
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2019-06-07 11:07:15 -07:00 |
Eddie Hung
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7057753427
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Rename label
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2019-05-21 18:20:31 -07:00 |
Eddie Hung
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b5a29460b9
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Try again
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2019-05-21 17:20:19 -07:00 |
Eddie Hung
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1bff09f2ff
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Fix warning
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2019-05-21 16:26:20 -07:00 |
Eddie Hung
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d9c915042a
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Move clean from aigerparse to abc9
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2019-04-23 13:42:35 -07:00 |
Eddie Hung
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5f30a8795d
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Tidy up
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2019-04-22 17:47:05 -07:00 |
Eddie Hung
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8f30019b68
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Revert "Temporarily remove 'r' extension"
This reverts commit eaf3c24772 .
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2019-04-22 17:41:21 -07:00 |
Eddie Hung
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eaf3c24772
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Temporarily remove 'r' extension
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2019-04-22 11:54:19 -07:00 |
Eddie Hung
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4883391b63
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Merge remote-tracking branch 'origin/master' into xaig
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2019-04-22 11:19:52 -07:00 |
Clifford Wolf
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e158ea2097
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Add log_debug() framework
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-22 17:25:52 +02:00 |
Eddie Hung
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21701cc1df
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read_aiger to parse 'r' extension
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2019-04-18 17:39:36 -07:00 |
Eddie Hung
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e1b550d203
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Ignore a/i/o/h XAIGER extensions
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2019-04-17 10:55:23 -07:00 |
Eddie Hung
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fecafb2207
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Forgot backslashes
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2019-04-12 18:22:44 -07:00 |
Eddie Hung
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9bfcd80063
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Handle __dummy_o__ and __const[01]__ in read_aiger not abc
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2019-04-12 18:21:16 -07:00 |
Eddie Hung
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c776db3320
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
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2019-04-12 17:09:24 -07:00 |
Eddie Hung
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acf3f5694b
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Fix inout handling for -map option
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2019-04-12 17:02:24 -07:00 |
Eddie Hung
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ada130b459
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Also cope with duplicated CIs
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2019-04-12 16:17:12 -07:00 |
Eddie Hung
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1c6f0cffd9
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Cope with an output having same name as an input (i.e. CO)
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2019-04-12 12:27:07 -07:00 |
Eddie Hung
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1a49cf29d8
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parse_aiger() to rename all $lut cells after "clean"
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2019-04-10 14:02:23 -07:00 |
Eddie Hung
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36efec01b8
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Fix spacing
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2019-04-08 16:37:22 -07:00 |
Eddie Hung
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da076344cc
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parse_xaiger() to really pass single and multi-bit inout tests
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2019-02-26 12:04:45 -08:00 |
Eddie Hung
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8f02c846f6
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parse_xaiger() to cope with multi bit inouts
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2019-02-26 11:37:34 -08:00 |
Eddie Hung
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316232a7dd
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parse_xaiger() to untransform $inout.out output ports
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2019-02-25 18:40:23 -08:00 |
Eddie Hung
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721f6a14fb
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read_aiger to accept empty string for clk_name, passable only if no latches
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2019-02-25 15:34:02 -08:00 |
Eddie Hung
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07036b8bf7
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read_aiger to work with symbol table
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2019-02-21 17:01:07 -08:00 |
Eddie Hung
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085ed9f487
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Add attribution
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2019-02-21 14:40:13 -08:00 |
Eddie Hung
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3307295488
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Merge branch 'read_aiger' into xaig
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2019-02-21 14:27:32 -08:00 |
Eddie Hung
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9e299a0908
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read_aiger to not do -purge for clean
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2019-02-20 17:33:04 -08:00 |
Eddie Hung
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32853b1f8d
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lut/not/and suffix to be ${lut,not,and}
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2019-02-20 16:30:30 -08:00 |
Eddie Hung
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abc1c2672e
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read_aiger to also rename 0 index lut when wideports
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2019-02-20 16:17:22 -08:00 |
Eddie Hung
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f9702a8abe
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read_aiger: new naming fixes
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2019-02-20 12:39:51 -08:00 |
Eddie Hung
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83b66861e9
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read_aiger to name wires with internal name, less likely to clash
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2019-02-20 11:22:56 -08:00 |
Eddie Hung
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7b026c4bc3
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Same for ascii AIGERs too
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2019-02-19 15:15:50 -08:00 |
Eddie Hung
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d304882cba
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read_aiger to cope with non-unique POs
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2019-02-19 15:14:08 -08:00 |
Eddie Hung
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e79df5e70e
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read_aiger to create sane $lut names, and rename when renaming driving wire
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2019-02-19 12:27:50 -08:00 |
Eddie Hung
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0b1fc46ae3
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Add comment
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2019-02-19 10:24:55 -08:00 |
Eddie Hung
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54f719f446
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Get rid of boost dep, fix the FIXMEs for Win32?
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2019-02-19 10:19:53 -08:00 |
Eddie Hung
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843e7fc8a7
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Fix for using POSIX basename
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2019-02-19 09:02:37 -08:00 |
Eddie Hung
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8e1dbfac3a
|
Missing OSX headers?
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2019-02-17 20:59:53 -08:00 |
Eddie Hung
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9268a271fb
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read_aiger to ignore line after ands for ascii, not binary
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2019-02-17 12:07:14 -08:00 |
Eddie Hung
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82459c16c4
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In read_xaiger, do not construct ConstEval for every LUT
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2019-02-16 22:22:29 -08:00 |
Eddie Hung
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f60cd4ff9b
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read_aiger to ignore output = input of same wire; also create new output for different wire
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2019-02-16 21:53:03 -08:00 |
Eddie Hung
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1a25ec4baa
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read_aiger to disable log_debug
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2019-02-16 13:45:51 -08:00 |
Eddie Hung
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8f36013fac
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read_xaiger() to use f.read() not readsome()
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2019-02-16 08:58:25 -08:00 |
Eddie Hung
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7523c87780
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read_aiger() to cope with constant outputs, mixed wideports, do cleaning
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2019-02-16 08:44:11 -08:00 |
Eddie Hung
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8d757224ee
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read_aiger with more asserts, and call clean
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2019-02-15 11:52:05 -08:00 |
Eddie Hung
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c7ef3863f3
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Leave FIXME for clean
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2019-02-13 17:19:30 -08:00 |
Eddie Hung
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396da54b52
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Use module->addLut()
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2019-02-13 17:08:32 -08:00 |
Eddie Hung
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13bf036bd6
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Use ConstEval to compute LUT masks
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2019-02-13 17:00:00 -08:00 |
Eddie Hung
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f0f5d8a5cc
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Merge remote-tracking branch 'origin/read_aiger' into xaig
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2019-02-13 14:09:36 -08:00 |
Eddie Hung
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e9df9a466a
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Add support for read_aiger -wideports
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2019-02-12 12:58:10 -08:00 |
Eddie Hung
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06ba81d41f
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Add support for read_aiger -map
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2019-02-12 12:16:37 -08:00 |
Eddie Hung
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77d3627753
|
Parse 'm' in xaiger
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2019-02-12 09:36:22 -08:00 |
Eddie Hung
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6faad18874
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Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger
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2019-02-12 09:21:46 -08:00 |
Eddie Hung
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a2ae393811
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Use module->add{Not,And}Gate() functions
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2019-02-12 09:21:15 -08:00 |
Eddie Hung
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0124512f28
|
Add read_xaiger
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2019-02-11 15:19:17 -08:00 |
Eddie Hung
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04c580fde7
|
Do not break for constraints
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2019-02-11 13:28:00 -08:00 |
Eddie Hung
|
727ba52504
|
No increment line_count for binary ANDs
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2019-02-11 13:24:21 -08:00 |
Eddie Hung
|
bb4164481d
|
Do not ignore newline after AND in binary AIG
|
2019-02-11 11:51:44 -08:00 |
Eddie Hung
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8886fa5506
|
addDff -> addDffGate as per @daveshah1
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2019-02-08 13:17:53 -08:00 |
Eddie Hung
|
afc3c4b613
|
Fix tabulation
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2019-02-08 13:17:02 -08:00 |
Eddie Hung
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aa66d8f12f
|
-module_name arg to go before -clk_name
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2019-02-08 12:49:55 -08:00 |
Eddie Hung
|
fb8ad440a3
|
Allow module name to be determined by argument too
|
2019-02-08 12:40:43 -08:00 |
Eddie Hung
|
f1befe1b44
|
Refactor into AigerReader class
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2019-02-08 12:04:26 -08:00 |
Eddie Hung
|
2a8cc36578
|
Parse binary AIG files
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2019-02-08 11:45:16 -08:00 |
Eddie Hung
|
09d758f0a3
|
Refactor to parse_aiger_header()
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2019-02-08 10:54:31 -08:00 |