mirror of https://github.com/YosysHQ/yosys.git
Read init from outputs
This commit is contained in:
parent
d969a9060e
commit
3d1185b835
|
@ -927,6 +927,10 @@ void AigerReader::post_process()
|
|||
}
|
||||
}
|
||||
log_debug(" -> %s\n", log_id(wire));
|
||||
int init;
|
||||
mf >> init;
|
||||
if (init < 2)
|
||||
wire->attributes["\\init"] = init;
|
||||
}
|
||||
else if (type == "box") {
|
||||
RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
|
||||
|
|
Loading…
Reference in New Issue