mirror of https://github.com/YosysHQ/yosys.git
Use ConstEval to compute LUT masks
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@ -24,6 +24,7 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "aigerparse.h"
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#include <boost/endian/buffers.hpp>
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@ -71,9 +72,9 @@ void AigerReader::parse_aiger()
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line_count = 1;
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if (header == "aag")
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parse_aiger_ascii(true /* create_and */);
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parse_aiger_ascii();
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else if (header == "aig")
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parse_aiger_binary(true /* create_and */);
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parse_aiger_binary();
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else
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log_abort();
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@ -123,6 +124,32 @@ static uint32_t parse_xaiger_literal(std::istream &f)
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return l.value();
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}
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static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal)
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{
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const unsigned variable = literal >> 1;
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const bool invert = literal & 1;
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RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix?
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RTLIL::Wire *wire = module->wire(wire_name);
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if (wire) return wire;
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log_debug("Creating %s\n", wire_name.c_str());
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wire = module->addWire(wire_name);
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if (!invert) return wire;
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RTLIL::IdString wire_inv_name(stringf("\\n%d", variable));
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RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
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if (wire_inv) {
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if (module->cell(wire_inv_name)) return wire;
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}
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else {
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log_debug("Creating %s\n", wire_inv_name.c_str());
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wire_inv = module->addWire(wire_inv_name);
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}
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log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
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module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix?
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return wire;
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}
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void AigerReader::parse_xaiger()
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{
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std::string header;
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@ -147,9 +174,9 @@ void AigerReader::parse_xaiger()
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line_count = 1;
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if (header == "aag")
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parse_aiger_ascii(false /* create_and */);
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parse_aiger_ascii();
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else if (header == "aig")
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parse_aiger_binary(false /* create_and */);
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parse_aiger_binary();
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else
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log_abort();
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@ -162,11 +189,11 @@ void AigerReader::parse_xaiger()
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if (!comment_seen) {
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f.ignore(1);
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c = f.peek();
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if (c == '\n')
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break;
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f.ignore(1);
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comment_seen = true;
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}
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if (c == '\n')
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break;
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f.ignore(1);
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// XAIGER extensions
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if (c == 'm') {
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uint32_t dataSize = parse_xaiger_literal(f);
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@ -178,7 +205,6 @@ void AigerReader::parse_xaiger()
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uint32_t cutLeavesM = parse_xaiger_literal(f);
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log_debug("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
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RTLIL::Wire *output_sig = module->wire(stringf("\\n%d", rootNodeID));
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log_assert(output_sig);
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uint32_t nodeID;
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RTLIL::SigSpec input_sig;
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for (unsigned j = 0; j < cutLeavesM; ++j) {
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@ -188,17 +214,30 @@ void AigerReader::parse_xaiger()
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log_assert(wire);
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input_sig.append(wire);
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}
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RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
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ConstEval ce(module);
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for (int j = 0; j < (1 << cutLeavesM); ++j) {
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ce.push();
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ce.set(input_sig, RTLIL::Const{j, static_cast<int>(cutLeavesM)});
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RTLIL::SigSpec o(output_sig);
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ce.eval(o);
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lut_mask[j] = o.as_const()[0];
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ce.pop();
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}
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RTLIL::Cell *output_cell = module->cell(stringf("\\n%d_and", rootNodeID));
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log_assert(output_cell);
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module->remove(output_cell);
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RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
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cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
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cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
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cell->parameters["\\LUT"] = std::move(lut_mask);
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cell->setPort("\\A", input_sig);
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cell->setPort("\\Y", output_sig);
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}
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}
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else if (c == 'n') {
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// TODO: What is this?
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uint32_t n = parse_xaiger_literal(f);
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f.seekg(n);
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parse_xaiger_literal(f);
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f >> s;
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log_debug("n: '%s'\n", s.c_str());
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}
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}
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else if (c == 'i' || c == 'l' || c == 'o') {
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@ -265,8 +304,7 @@ void AigerReader::parse_xaiger()
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}
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}
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for (auto &wp : wideports_cache)
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{
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for (auto &wp : wideports_cache) {
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auto name = wp.first;
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int width = wp.second + 1;
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@ -283,8 +321,10 @@ void AigerReader::parse_xaiger()
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wire->port_output = other_wire->port_output;
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other_wire->port_input = false;
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other_wire->port_output = false;
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if (wire->port_output)
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if (wire->port_input) {
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log_debug("assign %s = %s [%d];\n", other_wire->name.c_str(), wire->name.c_str(), i);
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module->connect(other_wire, SigSpec(wire, i));
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}
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else
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module->connect(SigSpec(wire, i), other_wire);
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}
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@ -295,33 +335,7 @@ void AigerReader::parse_xaiger()
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design->add(module);
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}
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static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal)
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{
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const unsigned variable = literal >> 1;
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const bool invert = literal & 1;
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RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix?
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RTLIL::Wire *wire = module->wire(wire_name);
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if (wire) return wire;
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log_debug("Creating %s\n", wire_name.c_str());
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wire = module->addWire(wire_name);
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if (!invert) return wire;
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RTLIL::IdString wire_inv_name(stringf("\\n%d", variable));
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RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
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if (wire_inv) {
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if (module->cell(wire_inv_name)) return wire;
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}
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else {
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log_debug("Creating %s\n", wire_inv_name.c_str());
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wire_inv = module->addWire(wire_inv_name);
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}
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log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
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module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix?
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return wire;
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}
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void AigerReader::parse_aiger_ascii(bool create_and)
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void AigerReader::parse_aiger_ascii()
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{
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std::string line;
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std::stringstream ss;
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@ -412,13 +426,11 @@ void AigerReader::parse_aiger_ascii(bool create_and)
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log_error("Line %u cannot be interpreted as an AND!\n", line_count);
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log_debug("%d %d %d is an AND\n", l1, l2, l3);
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if (create_and) {
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log_assert(!(l1 & 1));
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RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
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RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
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module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
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}
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log_assert(!(l1 & 1));
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RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
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RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
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module->addAndGate(o_wire->name.str() + "_and", i1_wire, i2_wire, o_wire);
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}
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}
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@ -431,7 +443,7 @@ static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
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return ref - (x | (ch << (7 * i)));
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}
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void AigerReader::parse_aiger_binary(bool create_and)
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void AigerReader::parse_aiger_binary()
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{
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unsigned l1, l2, l3;
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std::string line;
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@ -518,17 +530,11 @@ void AigerReader::parse_aiger_binary(bool create_and)
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l3 = parse_next_delta_literal(f, l2);
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log_debug("%d %d %d is an AND\n", l1, l2, l3);
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if (create_and) {
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log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
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RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
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RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
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RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
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and_cell->setPort("\\A", i1_wire);
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and_cell->setPort("\\B", i2_wire);
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and_cell->setPort("\\Y", o_wire);
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}
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log_assert(!(l1 & 1));
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RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
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RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
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module->addAndGate(o_wire->name.str() + "_and", i1_wire, i2_wire, o_wire);
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}
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}
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@ -44,8 +44,8 @@ struct AigerReader
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AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
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void parse_aiger();
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void parse_xaiger();
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void parse_aiger_ascii(bool create_and);
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void parse_aiger_binary(bool create_and);
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void parse_aiger_ascii();
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void parse_aiger_binary();
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};
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YOSYS_NAMESPACE_END
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