riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Cleanup

This commit is contained in:
Eddie Hung 2019-06-14 10:27:30 -07:00
parent 1948e7c846
commit a3be25ab0d
1 changed files with 3 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
frontends/aiger/aigerparse.cc
View File

@ -30,7 +30,7 @@
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/consteval.h"
#include "kernel/celltypes.h"
#include "aigerparse.h"
YOSYS_NAMESPACE_BEGIN
@ -44,15 +44,11 @@ struct ConstEvalAig
ConstEvalAig(RTLIL::Module *module) : module(module)
{
CellTypes ct;
ct.setup_internals();
ct.setup_stdcells();
for (auto &it : module->cells_) {
if (!ct.cell_known(it.second->type))
if (!yosys_celltypes.cell_known(it.second->type))
continue;
for (auto &it2 : it.second->connections())
if (ct.cell_output(it.second->type, it2.first)) {
if (yosys_celltypes.cell_output(it.second->type, it2.first)) {
auto r = sig2driver.insert(std::make_pair(it2.second, it.second));
log_assert(r.second);
}