mirror of https://github.com/YosysHQ/yosys.git
Reduce log_debug spam in parse_xaiger()
This commit is contained in:
Eddie Hung
parent
ad296d77ab
commit
f2ead4334a
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@ -52,6 +52,9 @@ inline int32_t from_big_endian(int32_t i32) {
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#endif
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}
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#define log_debug2(...) ;
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//#define log_debug2(...) log_debug(__VA_ARGS__)
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struct ConstEvalAig
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{
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RTLIL::Module *module;
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@ -312,7 +315,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
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RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : ""));
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RTLIL::Wire *wire = module->wire(wire_name);
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if (wire) return wire;
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log_debug("Creating %s\n", wire_name.c_str());
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log_debug2("Creating %s\n", wire_name.c_str());
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wire = module->addWire(wire_name);
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wire->port_input = wire->port_output = false;
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if (!invert) return wire;
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@ -322,12 +325,12 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
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if (module->cell(wire_inv_name)) return wire;
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}
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else {
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log_debug("Creating %s\n", wire_inv_name.c_str());
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log_debug2("Creating %s\n", wire_inv_name.c_str());
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wire_inv = module->addWire(wire_inv_name);
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wire_inv->port_input = wire_inv->port_output = false;
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}
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log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
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log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
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module->addNotGate(stringf("\\__%d__$not", variable), wire_inv, wire);
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return wire;
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@ -403,13 +406,13 @@ void AigerReader::parse_xaiger()
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for (unsigned i = 0; i < lutNum; ++i) {
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uint32_t rootNodeID = parse_xaiger_literal(f);
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uint32_t cutLeavesM = parse_xaiger_literal(f);
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log_debug("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
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log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
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RTLIL::Wire *output_sig = module->wire(stringf("\\__%d__", rootNodeID));
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uint32_t nodeID;
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RTLIL::SigSpec input_sig;
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for (unsigned j = 0; j < cutLeavesM; ++j) {
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nodeID = parse_xaiger_literal(f);
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log_debug("\t%u\n", nodeID);
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log_debug2("\t%u\n", nodeID);
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RTLIL::Wire *wire = module->wire(stringf("\\__%d__", nodeID));
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log_assert(wire);
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input_sig.append(wire);
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@ -493,7 +496,7 @@ void AigerReader::parse_aiger_ascii()
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for (unsigned i = 1; i <= I; ++i, ++line_count) {
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an input!\n", line_count);
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log_debug("%d is an input\n", l1);
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log_debug2("%d is an input\n", l1);
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log_assert(!(l1 & 1)); // Inputs can't be inverted
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RTLIL::Wire *wire = createWireIfNotExists(module, l1);
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wire->port_input = true;
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@ -506,7 +509,7 @@ void AigerReader::parse_aiger_ascii()
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log_assert(clk_name != "");
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clk_wire = module->wire(clk_name);
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log_assert(!clk_wire);
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log_debug("Creating %s\n", clk_name.c_str());
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log_debug2("Creating %s\n", clk_name.c_str());
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clk_wire = module->addWire(clk_name);
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clk_wire->port_input = true;
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clk_wire->port_output = false;
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@ -514,7 +517,7 @@ void AigerReader::parse_aiger_ascii()
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for (unsigned i = 0; i < L; ++i, ++line_count) {
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if (!(f >> l1 >> l2))
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log_error("Line %u cannot be interpreted as a latch!\n", line_count);
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log_debug("%d %d is a latch\n", l1, l2);
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log_debug2("%d %d is a latch\n", l1, l2);
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log_assert(!(l1 & 1));
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RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
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@ -548,7 +551,7 @@ void AigerReader::parse_aiger_ascii()
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an output!\n", line_count);
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log_debug("%d is an output\n", l1);
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log_debug2("%d is an output\n", l1);
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const unsigned variable = l1 >> 1;
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const bool invert = l1 & 1;
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RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
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@ -569,7 +572,7 @@ void AigerReader::parse_aiger_ascii()
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
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log_debug("%d is a bad state property\n", l1);
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log_debug2("%d is a bad state property\n", l1);
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RTLIL::Wire *wire = createWireIfNotExists(module, l1);
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wire->port_output = true;
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bad_properties.push_back(wire);
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@ -592,7 +595,7 @@ void AigerReader::parse_aiger_ascii()
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if (!(f >> l1 >> l2 >> l3))
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log_error("Line %u cannot be interpreted as an AND!\n", line_count);
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log_debug("%d %d %d is an AND\n", l1, l2, l3);
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log_debug2("%d %d %d is an AND\n", l1, l2, l3);
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log_assert(!(l1 & 1));
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RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
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@ -618,7 +621,7 @@ void AigerReader::parse_aiger_binary()
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// Parse inputs
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for (unsigned i = 1; i <= I; ++i) {
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log_debug("%d is an input\n", i);
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log_debug2("%d is an input\n", i);
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RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
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wire->port_input = true;
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log_assert(!wire->port_output);
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@ -631,7 +634,7 @@ void AigerReader::parse_aiger_binary()
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log_assert(clk_name != "");
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clk_wire = module->wire(clk_name);
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log_assert(!clk_wire);
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log_debug("Creating %s\n", clk_name.c_str());
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log_debug2("Creating %s\n", clk_name.c_str());
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clk_wire = module->addWire(clk_name);
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clk_wire->port_input = true;
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clk_wire->port_output = false;
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@ -673,7 +676,7 @@ void AigerReader::parse_aiger_binary()
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an output!\n", line_count);
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log_debug("%d is an output\n", l1);
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log_debug2("%d is an output\n", l1);
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const unsigned variable = l1 >> 1;
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const bool invert = l1 & 1;
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RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_b" the right suffix?
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@ -695,7 +698,7 @@ void AigerReader::parse_aiger_binary()
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
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log_debug("%d is a bad state property\n", l1);
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log_debug2("%d is a bad state property\n", l1);
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RTLIL::Wire *wire = createWireIfNotExists(module, l1);
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wire->port_output = true;
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bad_properties.push_back(wire);
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@ -721,7 +724,7 @@ void AigerReader::parse_aiger_binary()
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l2 = parse_next_delta_literal(f, l1);
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l3 = parse_next_delta_literal(f, l2);
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log_debug("%d %d %d is an AND\n", l1, l2, l3);
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log_debug2("%d %d %d is an AND\n", l1, l2, l3);
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log_assert(!(l1 & 1));
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RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
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