parse_xaiger to cope with inouts

This commit is contained in:
Eddie Hung 2019-06-12 15:45:46 -07:00
parent fb2758aade
commit 342fc0a600
1 changed files with 0 additions and 6 deletions

View File

@ -696,10 +696,6 @@ void AigerReader::post_process()
RTLIL::Wire* wire = outputs[variable + co_count];
log_assert(wire);
log_assert(wire->port_output);
if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) {
wire->port_output = false;
continue;
}
if (index == 0) {
// Cope with the fact that a CO might be identical
@ -797,8 +793,6 @@ void AigerReader::post_process()
port_output = port_output || other_wire->port_output;
}
}
if ((port_input && port_output) || (!port_input && !port_output))
continue;
wire = module->addWire(name, width);
wire->port_input = port_input;