mirror of https://github.com/YosysHQ/yosys.git
parse_xaiger to cope with inouts
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@ -696,10 +696,6 @@ void AigerReader::post_process()
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RTLIL::Wire* wire = outputs[variable + co_count];
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log_assert(wire);
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log_assert(wire->port_output);
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if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) {
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wire->port_output = false;
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continue;
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}
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if (index == 0) {
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// Cope with the fact that a CO might be identical
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@ -797,8 +793,6 @@ void AigerReader::post_process()
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port_output = port_output || other_wire->port_output;
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}
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}
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if ((port_input && port_output) || (!port_input && !port_output))
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continue;
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wire = module->addWire(name, width);
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wire->port_input = port_input;
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