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read_aiger to also rename 0 index lut when wideports

This commit is contained in:
Eddie Hung 2019-02-20 16:17:22 -08:00
parent 01f8d50ba2
commit abc1c2672e
1 changed files with 14 additions and 2 deletions
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16
frontends/aiger/aigerparse.cc
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@ -162,9 +162,15 @@ void AigerReader::parse_aiger()
int width = wp.second + 1;
RTLIL::Wire *wire = module->wire(name);
if (wire)
if (wire) {
RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str()));
module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
if (driver)
module->rename(driver, stringf("%slut", wire->name.c_str()));
}
// Do not make ports with a mix of input/output into
// wide ports
bool port_input = false, port_output = false;
@ -408,9 +414,15 @@ void AigerReader::parse_xaiger()
int width = wp.second + 1;
RTLIL::Wire *wire = module->wire(name);
if (wire)
if (wire) {
RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str()));
module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
if (driver)
module->rename(driver, stringf("%slut", wire->name.c_str()));
}
// Do not make ports with a mix of input/output into
// wide ports
bool port_input = false, port_output = false;