mirror of https://github.com/YosysHQ/yosys.git
Temporarily remove 'r' extension
This commit is contained in:
Eddie Hung
parent
b780c0a7de
commit
eaf3c24772
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@ -50,7 +50,6 @@ struct XAigerWriter
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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//pool<SigBit> initstate_bits;
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vector<std::pair<SigBit,int>> ci_bits, co_bits;
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vector<std::pair<SigBit,SigBit>> ff_bits;
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vector<pair<int, int>> aig_gates;
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vector<int> aig_latchin, aig_latchinit, aig_outputs;
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@ -175,7 +174,6 @@ struct XAigerWriter
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for (auto cell : module->cells())
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{
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RTLIL::Module* inst_module = module->design->module(cell->type);
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bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
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bool known_type = yosys_celltypes.cell_known(cell->type);
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if (!holes_mode) {
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@ -252,32 +250,7 @@ struct XAigerWriter
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// continue;
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//}
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if (inst_flop) {
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SigBit d, q;
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for (const auto &c : cell->connections()) {
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for (auto b : c.second.bits()) {
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auto is_input = cell->input(c.first);
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auto is_output = cell->output(c.first);
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log_assert(is_input || is_output);
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if (is_input && inst_module->wire(c.first)->attributes.count("\\abc_flop_d")) {
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SigBit I = sigmap(b);
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if (I != b)
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alias_map[b] = I;
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d = b;
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}
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if (is_output && inst_module->wire(c.first)->attributes.count("\\abc_flop_q")) {
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SigBit O = sigmap(b);
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q = O;
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}
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}
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}
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if (!abc_box_seen)
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abc_box_seen = inst_module->attributes.count("\\abc_box_id");
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ff_bits.emplace_back(d, q);
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undriven_bits.erase(q);
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}
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else if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
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if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
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abc_box_seen = true;
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}
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else {
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@ -420,20 +393,10 @@ struct XAigerWriter
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aig_map[bit] = 2*aig_m;
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}
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for (auto &f : ff_bits) {
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auto bit = f.second;
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aig_m++, aig_i++;
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aig_map[bit] = 2*aig_m;
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}
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dict<SigBit, int> ff_aig_map;
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for (auto &c : ci_bits) {
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aig_m++, aig_i++;
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c.second = 2*aig_m;
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auto r = aig_map.insert(std::make_pair(c.first, c.second));
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if (!r.second) {
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ff_aig_map[c.first] = c.second;
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}
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aig_map[c.first] = c.second;
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}
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if (imode && input_bits.empty()) {
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@ -508,11 +471,6 @@ struct XAigerWriter
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aig_outputs.push_back(bit2aig(bit));
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}
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for (auto &f : ff_bits) {
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aig_o++;
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aig_outputs.push_back(ff_aig_map.at(f.second));
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}
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if (omode && output_bits.empty()) {
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aig_o++;
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aig_outputs.push_back(0);
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@ -670,7 +628,7 @@ struct XAigerWriter
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f << "c";
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if (!box_list.empty() || !ff_bits.empty()) {
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if (!box_list.empty()) {
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std::stringstream h_buffer;
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auto write_h_buffer = [&h_buffer](int i32) {
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// TODO: Don't assume we're on little endian
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@ -685,10 +643,10 @@ struct XAigerWriter
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if (omode && num_outputs == 0)
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num_outputs = 1;
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write_h_buffer(1);
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write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
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write_h_buffer(num_outputs + ff_bits.size() + co_bits.size());
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write_h_buffer(input_bits.size() + ff_bits.size());
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write_h_buffer(num_outputs + ff_bits.size());
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write_h_buffer(input_bits.size() + ci_bits.size());
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write_h_buffer(num_outputs + co_bits.size());
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write_h_buffer(input_bits.size());
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write_h_buffer(num_outputs);
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write_h_buffer(box_list.size());
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RTLIL::Module *holes_module = nullptr;
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@ -741,34 +699,6 @@ struct XAigerWriter
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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if (!ff_bits.empty()) {
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std::stringstream r_buffer;
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auto write_r_buffer = [&r_buffer](int i32) {
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// TODO: Don't assume we're on little endian
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#ifdef _WIN32
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int i32_be = _byteswap_ulong(i32);
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#else
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int i32_be = __builtin_bswap32(i32);
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#endif
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r_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
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};
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write_r_buffer(ff_bits.size());
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int mergeability_class = 1;
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for (auto cell : ff_bits)
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write_r_buffer(mergeability_class++);
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f << "r";
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std::string buffer_str = r_buffer.str();
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// TODO: Don't assume we're on little endian
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#ifdef _WIN32
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int buffer_size_be = _byteswap_ulong(buffer_str.size());
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#else
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int buffer_size_be = __builtin_bswap32(buffer_str.size());
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#endif
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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}
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if (holes_module) {
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holes_module->fixup_ports();
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@ -360,24 +360,6 @@ void AigerReader::parse_xaiger()
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module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
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}
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}
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else if (c == 'r') {
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uint32_t dataSize = parse_xaiger_literal(f);
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uint32_t flopNum = parse_xaiger_literal(f);
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f.ignore(flopNum * sizeof(uint32_t));
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log_assert(inputs.size() >= flopNum);
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for (auto it = inputs.end() - flopNum; it != inputs.end(); ++it) {
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log_assert((*it)->port_input);
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(*it)->port_input = false;
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}
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inputs.erase(inputs.end() - flopNum, inputs.end());
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log_assert(outputs.size() >= flopNum);
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for (auto it = outputs.end() - flopNum; it != outputs.end(); ++it) {
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log_assert((*it)->port_output);
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(*it)->port_output = false;
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}
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outputs.erase(outputs.end() - flopNum, outputs.end());
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module->fixup_ports();
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}
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else if (c == 'n') {
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parse_xaiger_literal(f);
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f >> s;
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