riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Missing close bracket

This commit is contained in:
Eddie Hung 2019-06-15 09:10:01 -07:00
parent 295bb23ae0
commit 7a3c403ba0
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
frontends/aiger/aigerparse.cc
View File

@ -1025,7 +1025,7 @@ struct AigerFrontend : public Frontend {
log(" Name of module to be created (default: <filename>)\n");
log("\n");
log(" -clk_name <wire_name>\n");
log(" If specified, AIGER latches to be transformed into $_DFF_P_ cells\n"
log(" If specified, AIGER latches to be transformed into $_DFF_P_ cells\n");
log(" clocked by wire of this name. Otherwise, $_FF_ cells will be used.\n");
log("\n");
log(" -map <filename>\n");