mirror of https://github.com/YosysHQ/yosys.git
In read_xaiger, do not construct ConstEval for every LUT
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@ -290,6 +290,7 @@ void AigerReader::parse_xaiger()
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uint32_t lutNum = parse_xaiger_literal(f);
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uint32_t lutSize = parse_xaiger_literal(f);
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log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
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ConstEval ce(module);
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for (unsigned i = 0; i < lutNum; ++i) {
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uint32_t rootNodeID = parse_xaiger_literal(f);
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uint32_t cutLeavesM = parse_xaiger_literal(f);
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@ -305,7 +306,6 @@ void AigerReader::parse_xaiger()
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input_sig.append(wire);
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}
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RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
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ConstEval ce(module);
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for (int j = 0; j < (1 << cutLeavesM); ++j) {
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ce.push();
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ce.set(input_sig, RTLIL::Const{j, static_cast<int>(cutLeavesM)});
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