mirror of https://github.com/YosysHQ/yosys.git
read_aiger to disable log_debug
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@ -33,6 +33,7 @@
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YOSYS_NAMESPACE_BEGIN
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#define log_debug log
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#define log_debug(...) ;
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AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports)
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: design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports)
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@ -627,8 +628,8 @@ void AigerReader::parse_aiger_binary()
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log_debug("%d is an output\n", l1);
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wire = createWireIfNotExists(module, l1);
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}
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wire->port_output = true;
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log_assert(!wire->port_input);
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wire->port_output = true;
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outputs.push_back(wire);
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}
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std::getline(f, line); // Ignore up to start of next line
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