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Use module->addLut()

This commit is contained in:
Eddie Hung 2019-02-13 17:08:32 -08:00
parent 206f11dca3
commit 396da54b52
1 changed files with 1 additions and 5 deletions
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6
frontends/aiger/aigerparse.cc
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@ -227,11 +227,7 @@ void AigerReader::parse_xaiger()
RTLIL::Cell *output_cell = module->cell(stringf("\\n%d_and", rootNodeID));
log_assert(output_cell);
module->remove(output_cell);
RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
cell->parameters["\\LUT"] = std::move(lut_mask);
cell->setPort("\\A", input_sig);
cell->setPort("\\Y", output_sig);
module->addLut(NEW_ID, input_sig, output_sig, std::move(lut_mask));
}
}
else if (c == 'n') {