mirror of https://github.com/YosysHQ/yosys.git
Fix spacing
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bca3cf6843
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@ -805,13 +805,13 @@ struct AigerFrontend : public Frontend {
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log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
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log(" this name (default: clk)\n");
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log("\n");
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log(" -map <filename>\n");
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log(" read file with port and latch symbols\n");
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log(" -map <filename>\n");
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log(" read file with port and latch symbols\n");
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log("\n");
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log(" -wideports\n");
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log(" Merge ports that match the pattern 'name[int]' into a single\n");
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log(" multi-bit port 'name'.\n");
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log("\n");
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log(" -wideports\n");
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log(" Merge ports that match the pattern 'name[int]' into a single\n");
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log(" multi-bit port 'name'.\n");
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log("\n");
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}
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void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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@ -822,28 +822,28 @@ struct AigerFrontend : public Frontend {
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std::string map_filename;
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bool wideports = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if (arg == "-module_name" && argidx+1 < args.size()) {
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module_name = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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if (arg == "-clk_name" && argidx+1 < args.size()) {
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clk_name = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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if (map_filename.empty() && arg == "-map" && argidx+1 < args.size()) {
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map_filename = args[++argidx];
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continue;
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}
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if (arg == "-wideports") {
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wideports = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if (arg == "-module_name" && argidx+1 < args.size()) {
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module_name = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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if (arg == "-clk_name" && argidx+1 < args.size()) {
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clk_name = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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if (map_filename.empty() && arg == "-map" && argidx+1 < args.size()) {
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map_filename = args[++argidx];
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continue;
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}
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if (arg == "-wideports") {
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wideports = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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if (module_name.empty()) {
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#ifdef _WIN32
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@ -858,7 +858,7 @@ struct AigerFrontend : public Frontend {
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}
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AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports);
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reader.parse_aiger();
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reader.parse_aiger();
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}
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} AigerFrontend;
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