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Use module->add{Not,And}Gate() functions

This commit is contained in:
Eddie Hung 2019-02-12 09:21:15 -08:00
parent fb6df09dd2
commit a2ae393811
1 changed files with 2 additions and 8 deletions
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10
frontends/aiger/aigerparse.cc
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@ -134,9 +134,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
}
log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
RTLIL::Cell *inv = module->addCell(stringf("\\n%d_not", variable), "$_NOT_"); // FIXME: is "_not" the right suffix?
inv->setPort("\\A", wire_inv);
inv->setPort("\\Y", wire);
module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix?
return wire;
}
@ -236,11 +234,7 @@ void AigerReader::parse_aiger_ascii()
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
and_cell->setPort("\\A", i1_wire);
and_cell->setPort("\\B", i2_wire);
and_cell->setPort("\\Y", o_wire);
module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
}
std::getline(f, line); // Ignore up to start of next line
}