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1710 Commits

Author SHA1 Message Date
Eddie Hung fb203d2a2c ice40_opt to restore attributes/name when unwrapping 2019-12-09 14:29:29 -08:00
Eddie Hung 500ed9b501 Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 2019-12-09 12:45:22 -08:00
Eddie Hung e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00
David Shah 184c0e796a ecp5: Add support for mapping PRLD FFs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-07 13:04:36 +00:00
Eddie Hung a46a7e8a67 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-06 23:22:52 -08:00
Eddie Hung 98c9ea605b techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger 2019-12-06 17:05:02 -08:00
Eddie Hung c767525441 Remove creation of $abc9_control_wire 2019-12-06 16:23:09 -08:00
Eddie Hung ec0acc9f85 abc9 to use mergeability class to differentiate sync/async 2019-12-06 00:12:37 -08:00
Eddie Hung 02786b0aa0 Remove clkpart 2019-12-05 17:25:26 -08:00
Eddie Hung 864bff14f1 Revert "Special abc9_clock wire to contain only clock signal" 
This reverts commit 6a2eb5d8f9.
 2019-12-05 11:11:53 -08:00
Eddie Hung 0d248dd7ba Missing wire declaration 2019-12-04 23:04:40 -08:00
Eddie Hung 19bc429482 abc9_map.v to transform INIT=1 to INIT=0 2019-12-04 21:36:41 -08:00
Eddie Hung 258a34e6f1 Oh deary me 2019-12-04 20:33:24 -08:00
Eddie Hung b43986c5a1 output reg Q -> output Q to suppress warning 2019-12-04 16:34:34 -08:00
Eddie Hung 31ef4cc704 abc9_map.v to do `zinit' and make INIT = 1'b0 2019-12-04 16:11:02 -08:00
Marcin Kościelnicki fcce94010f
xilinx: Add tristate buffer mapping. (#1528) 
Fixes #1225.
 2019-12-04 09:44:00 +01:00
Marcin Kościelnicki 10014e2643
xilinx: Add models for LUTRAM cells. (#1537) 2019-12-04 06:31:09 +01:00
Eddie Hung a181ff66d3 Add abc9_init wire, attach to abc9_flop cell 2019-12-03 18:47:09 -08:00
Eddie Hung f98aa1c13f Revert "Add INIT value to abc9_control" 
This reverts commit 19bfb41958.
 2019-12-03 15:40:44 -08:00
Eddie Hung ed3f359175 $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve 
name and attr
 2019-12-03 14:49:10 -08:00
Eddie Hung 1ea9ce0ad7 ice40_opt to ignore (* keep *) -ed cells 2019-12-03 14:48:39 -08:00
Eddie Hung 0add5965c7 techmap abc_unmap.v before xilinx_srl -fixed 2019-12-03 14:27:45 -08:00
Clifford Wolf 2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit 
Gowin: add and test DFF init values
 2019-12-03 08:43:18 -08:00
Pepijn de Vos a3b25b4af8 Use -match-init to not synth contradicting init values 2019-12-03 15:12:25 +01:00
Eddie Hung 19bfb41958 Add INIT value to abc9_control 2019-12-02 14:17:06 -08:00
Marcin Kościelnicki 2badaa9adb xilinx: Add missing blackbox cell for BUFPLL. 2019-11-29 16:56:27 +01:00
Eddie Hung b1ab7c16c4 clkpart -unpart into 'finalize' 2019-11-28 12:59:43 -08:00
Diego H 3a5a65829c Adjusting Vivado's BRAM min bits threshold for RAMB18E1 2019-11-27 12:05:04 -06:00
Eddie Hung df8dc6d1fb ean call after abc{,9} 2019-11-27 09:10:34 -08:00
Eddie Hung f6c0ec1d09 Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff 2019-11-27 01:03:33 -08:00
Eddie Hung 739f530906 Move 'clean' from map_luts to finalize 2019-11-26 14:51:39 -08:00
Marcin Kościelnicki 0466c48533 xilinx: Add simulation models for IOBUF and OBUFT. 2019-11-26 08:15:20 +01:00
Eddie Hung d087024caf Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-25 12:42:09 -08:00
Eddie Hung 6a2eb5d8f9 Special abc9_clock wire to contain only clock signal 2019-11-25 12:36:13 -08:00
Marcin Kościelnicki 6cdea425b8 clkbufmap: Add support for inverters in clock path. 2019-11-25 20:40:39 +01:00
Marcin Kościelnicki 7562e7304e xilinx: Use INV instead of LUT1 when applicable 2019-11-25 20:40:39 +01:00
Pepijn de Vos 72d03dc910 attempt to fix formatting 2019-11-25 14:50:34 +01:00
Pepijn de Vos 6c79abbf5a gowin: add and test dff init values 2019-11-25 14:33:21 +01:00
Eddie Hung eb11c06a69 For abc9, run clkpart before ff_map and after abc9 2019-11-23 10:18:22 -08:00
Martin Pietryka 97b22413e5 coolrunner2: remove spurious log_pop() call, fixes #1463 
This was causing a segmentation fault because there is no accompanying
log_push() call so header_count.size() became -1.

Signed-off-by: Martin Pietryka <martin@pietryka.at>
 2019-11-23 06:21:40 +01:00
Eddie Hung bd56161775 Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:38:48 -08:00
Marcin Kościelnicki 1d098b7195 gowin: Add missing .gitignore entries 2019-11-22 14:40:36 +01:00
Eddie Hung 5a30e3ac3b Merge branch 'eddie/xaig_dff_adff' into xaig_dff 2019-11-21 16:15:25 -08:00
Eddie Hung af3055fe83 Add blackbox model for $__ABC9_FF_ so that clock partitioning works 2019-11-20 14:30:56 -08:00
Eddie Hung df63d75ff3 Fix INIT values 2019-11-20 11:26:59 -08:00
Eddie Hung 344619079d Do not drop async control signals in abc_map.v 2019-11-19 16:57:07 -08:00
Eddie Hung 09ee96e8c2 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-19 15:40:39 -08:00
Clifford Wolf 7ea0a5937b
Merge pull request #1449 from pepijndevos/gowin 
Improvements for gowin support
 2019-11-19 17:29:27 +01:00
Pepijn de Vos 8ab412eb16 Remove dff init altogether 
The hardware does not actually support it.
In reality it is always initialised to its reset value.
 2019-11-19 15:53:44 +01:00
Marcin Kościelnicki 7a9081440c xilinx: Add simulation models for MULT18X18* and DSP48A*. 
This adds simulation models for the following primitives:

- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
 2019-11-19 01:00:58 +01:00
Pepijn de Vos dd8c7e1ddd add help for nowidelut and abc9 options 2019-11-18 14:26:09 +01:00
Pepijn de Vos 32f0296df1 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-11-16 12:43:17 +01:00
David Shah 51e4e29bb1 ecp5: Use new autoname pass for better cell/net names 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-15 21:03:11 +00:00
Clifford Wolf e907ee4fde
Merge pull request #1490 from YosysHQ/clifford/autoname 
Add "autoname" pass and use it in "synth_ice40"
 2019-11-14 18:03:44 +01:00
Clifford Wolf 056ef76711
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim 
ice40: Support for post-place-and-route timing simulations
 2019-11-14 12:07:25 +01:00
Clifford Wolf 07c854b7af Add "autoname" pass and use it in "synth_ice40" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-13 13:41:16 +01:00
Pepijn de Vos ab8c521030 fix fsm test with proper clock enable polarity 2019-11-11 17:51:26 +01:00
Pepijn de Vos ec3faa7b96 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-11-11 17:08:40 +01:00
Clifford Wolf 362f4f996d Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-11 15:07:29 +01:00
Pepijn de Vos 0e5dbc4abc fix wide luts 2019-11-06 19:48:18 +01:00
Marcin Kościelnicki c4bd318e76 synth_xilinx: Merge blackbox primitive libraries. 
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.

Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included.  Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.

Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).

Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
 2019-11-06 15:11:27 +01:00
Pepijn de Vos 0f6269b04c add IOBUF 2019-10-28 15:33:05 +01:00
Pepijn de Vos 903f997391 add tristate buffer and test 2019-10-28 15:18:01 +01:00
Pepijn de Vos 2f5e9e9885 More formatting 2019-10-28 13:10:12 +01:00
Pepijn de Vos c1921b4561 really really fix formatting maybe 2019-10-28 13:01:20 +01:00
Pepijn de Vos 293b2c2de5 undo formatting fuckup 2019-10-28 12:57:12 +01:00
Pepijn de Vos f88335a8a5 add wide luts 2019-10-28 12:49:08 +01:00
Pepijn de Vos 5fad53b504 add 32-bit BRAM and byte-enables 2019-10-28 10:33:27 +01:00
Pepijn de Vos 8226f2db0b ALU sim tweaks 2019-10-24 13:39:43 +02:00
David Shah e135ed5d80 ice40: Add post-pnr ICESTORM_RAM model and fix FFs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 18:44:34 +01:00
David Shah 37dd3ad3fe ice40: Support for post-pnr timing simulation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 12:03:31 +01:00
David Shah 3506eaf290 xilinx: Add URAM288 mapping for xcup 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 11:47:44 +01:00
David Shah 6769d31ddb xilinx: Add support for UltraScale[+] BRAM mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 11:47:37 +01:00
Marcin Kościelnicki 7b350cacd4 xilinx: Support multiplier mapping for all families. 
This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
 2019-10-22 18:06:57 +02:00
Clifford Wolf a3a7bb9bf7
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg 
Call memory_dff before DSP mapping to reserve registers (fixes #1447)
 2019-10-22 17:36:54 +02:00
Pepijn de Vos 03457ee13e add a few more missing dff 2019-10-21 16:08:13 +02:00
Pepijn de Vos 8a2699c40c add negedge DFF 2019-10-21 12:31:11 +02:00
Pepijn de Vos af7bdd598e use ADDSUB ALU mode to remove inverters 2019-10-21 12:00:27 +02:00
Pepijn de Vos 69fb3b8db2 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-10-21 10:51:34 +02:00
David Shah fa989e59e5 ecp5: Pass -nomfs to abc9 
Fixes #1459

Signed-off-by: David Shah <dave@ds0.me>
 2019-10-20 10:30:41 +01:00
Sean Cross 82f60ba938 Makefile: don't assume python is called `python3` 
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`.  The build system assumes
that python is called `python3`, which breaks under this architecture.

There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS.  Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.

Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-19 14:04:52 +08:00
Miodrag Milanović b4d7650548
Merge branch 'master' into mmicko/efinix 2019-10-18 10:54:28 +02:00
N. Engelhardt 3b405d985e Call memory_dff before DSP mapping to reserve registers (fixes #1447) 2019-10-17 21:33:54 +02:00
Pepijn de Vos 72323e11a4 remove duplicate DFFR 2019-10-16 11:24:56 +02:00
David Shah e1d4e683b4 ecp5: Add ECLKBRIDGECS blackbox 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-11 14:50:33 +01:00
David Shah 7b1a6706d8 ecp5: Add attrmvcp to copy syn_useioff to driving FF 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-10 15:58:31 +01:00
David Shah 3b44e80d4b ecp5: Set syn_useioff on IO FFs to enable packing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-10 15:55:16 +01:00
Marcin Kościelnicki 526fe4cb89 xilinx: Add simulation model for IBUFG. 2019-10-10 13:16:03 +02:00
Eddie Hung 304e5f9ea4 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-08 13:03:06 -07:00
Eddie Hung 9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 
Rename abc_* names/attributes to more precisely be abc9_*
 2019-10-08 10:53:38 -07:00
Eddie Hung 4f0818275f Cleanup 2019-10-07 15:58:55 -07:00
Eddie Hung b2e34f932a Rename $currQ to $abc9_currQ 2019-10-07 15:31:43 -07:00
Eddie Hung bae3d8705d Update comments in abc9_map.v 2019-10-07 12:54:45 -07:00
Eddie Hung 1dc22607c3 Remove -D_ABC9 2019-10-07 12:21:52 -07:00
Eddie Hung 3879ca1398 Do not require changes to cells_sim.v; try and work out comb model 2019-10-05 22:55:18 -07:00
Eddie Hung 6c5e1234e1 Add comment on why partial multipliers are 18x18 2019-10-04 22:31:04 -07:00
Eddie Hung b47bb5c810 Fix typo in check_label() 2019-10-04 21:43:50 -07:00
Eddie Hung a2ef93f03a abc -> abc9 2019-10-04 17:56:38 -07:00
Eddie Hung a5ac33f230 Merge branch 'master' into eddie/abc_to_abc9 2019-10-04 17:53:20 -07:00
Eddie Hung bbc0e06af3 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-04 17:39:08 -07:00
Eddie Hung 0acc51c3d8 Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` 2019-10-04 17:35:43 -07:00
Eddie Hung d4212d128b Use read_args for read_verilog 2019-10-04 17:27:05 -07:00
Eddie Hung 9c23811839 Remove DSP48E1 from *_cells_xtra.v 2019-10-04 17:26:42 -07:00
Eddie Hung 7959e9d6b2 Fix merge issues 2019-10-04 17:21:14 -07:00
Eddie Hung 7a45cd5856 Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff 2019-10-04 16:58:55 -07:00
Eddie Hung aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung 9fef1df3c1 Panic over. Model was elsewhere. Re-arrange for consistency 2019-10-04 10:48:44 -07:00
Eddie Hung 4e11782cde Oops 2019-10-04 10:36:02 -07:00
Eddie Hung c0f54d3fd5 Ohmilord this wasn't added all this time!?! 2019-10-04 10:34:16 -07:00
Miodrag Milanovic 44c3472b9f FF should be initialized to 0 2019-10-04 13:27:10 +02:00
Miodrag Milanovic 77d557d00b Add missing latch mapping 2019-10-04 12:58:11 +02:00
Eddie Hung 549d6ea467 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-03 10:55:23 -07:00
Eddie Hung 655f1b2ac5 English 2019-10-03 10:11:25 -07:00
Eddie Hung 5299884f04 More fixes 2019-10-01 13:41:08 -07:00
Eddie Hung 03ebe43e3e Escape Verilog identifiers for legality outside of Yosys 2019-10-01 13:05:56 -07:00
David Shah b424d374db ecp5: Fix shuffle_enable port 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 14:14:46 +01:00
David Shah 7a1538cd36 ecp5: Add support for mapping 36-bit wide PDP BRAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 13:46:36 +01:00
Eddie Hung e529872b01 Remove need for $currQ port connection 2019-09-30 16:33:40 -07:00
Eddie Hung 5e9ae90cbb Add explanation to abc_map.v 2019-09-30 15:39:24 -07:00
Eddie Hung 8684b58bed Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-30 12:29:35 -07:00
Eddie Hung 5b5756b91e Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} 2019-09-30 12:52:43 +02:00
Marcin Kościelnicki 4535f2c694 synth_xilinx: Support latches, remove used-up FF init values. 
Fixes #1387.
 2019-09-30 12:52:43 +02:00
Eddie Hung f6203e6bd6 Missing endmodule 2019-09-29 21:55:53 -07:00
Eddie Hung 1123c09588 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 19:39:12 -07:00
Eddie Hung 8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Eddie Hung 18ebb86edb FDCE_1 does not have IS_CLR_INVERTED 2019-09-29 11:25:34 -07:00
Eddie Hung f3e150d9a5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 09:21:51 -07:00
Eddie Hung 79b6edb639 Big rework; flop info now mostly in cells_sim.v 2019-09-28 23:48:17 -07:00
Eddie Hung c372e7baf9 Fix box name 2019-09-27 18:49:45 -07:00
Eddie Hung 8f5710c464 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-27 15:14:31 -07:00
Eddie Hung b3d8a60cbd Re-order 2019-09-27 14:32:07 -07:00
Eddie Hung 90236025b7 Missing (* mul2dsp *) for sliceB 2019-09-27 14:21:47 -07:00
Eddie Hung 143f82def2 Missing an '&' 2019-09-26 11:13:08 -07:00
Eddie Hung 84825f9378 Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once 2019-09-26 10:45:14 -07:00
Eddie Hung 033aefc0f4 Typo 2019-09-26 10:34:14 -07:00
Eddie Hung 781dda6175 select once 2019-09-26 10:15:05 -07:00
Eddie Hung 27e5bf5aad Stop trying to be too smart by prematurely optimising 2019-09-26 09:57:11 -07:00
Eddie Hung 35aaa8d73a mul2dsp.v slice names 2019-09-25 22:58:55 -07:00
Eddie Hung 34aa3532fb Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit 2019-09-25 17:26:47 -07:00
Eddie Hung a4238637ac Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" 
This reverts commit 234738b103.
 2019-09-25 17:25:44 -07:00
Eddie Hung f4387e817c Revert "No need for $__mul anymore?" 
This reverts commit 1d875ac76a.
 2019-09-25 17:24:11 -07:00
Eddie Hung 63940913d2 Only wreduce on t:$add 2019-09-25 17:22:04 -07:00
Eddie Hung 234738b103 Remove _TECHMAP_CELLTYPE_ check since all $mul 2019-09-25 16:51:31 -07:00
Eddie Hung 1d875ac76a No need for $__mul anymore? 2019-09-25 14:06:21 -07:00
Eddie Hung 53ea5daa42 Call 'wreduce' after mul2dsp to avoid unextend() 2019-09-25 14:04:36 -07:00
Eddie Hung 93363c94a2 Oops. Actually use __NAME__ in ABC_DSP48E1 macro 2019-09-25 10:33:16 -07:00
Eddie Hung b41d2fb4e4 Add (* techmap_autopurge *) to abc_unmap.v too 2019-09-23 22:02:22 -07:00
Eddie Hung 11ac37733d Add techmap_autopurge to outputs in abc_map.v too 2019-09-23 21:56:28 -07:00
Eddie Hung 27167848f4 Revert "Add a xilinx_finalise pass" 
This reverts commit 23d90e0439.
 2019-09-23 19:52:55 -07:00
Eddie Hung 0f53893104 Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" 
This reverts commit 67c2db3486.
 2019-09-23 19:52:55 -07:00