Marcelina Kościelnicka
9a4f420b4b
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka
6cd135a5eb
opt_expr: Remove -clkinv option, make it the default.
...
Adds -noclkinv option just in case the old behavior was actually useful
to someone.
2020-07-31 00:08:15 +02:00
Marcelina Kościelnicka
cf60699884
synth_ice40: Use opt_dff.
...
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:20 +02:00
Marcelina Kościelnicka
8501342fc5
synth_xilinx: Use opt_dff.
...
The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:09 +02:00
Dan Ravensloft
a2fb84fd0c
intel_alm: direct M10K instantiation
...
This reverts commit a3a90f6377
.
2020-07-27 15:39:06 +02:00
Dan Ravensloft
62311b7ec0
intel_alm: increase abc9 -W
2020-07-26 23:56:54 +02:00
Marcelina Kościelnicka
0c6d0d4b5d
satgen: Add support for dffe, sdff, sdffe, sdffce cells.
2020-07-24 03:19:21 +02:00
Dan Ravensloft
4d9d90079c
intel_alm: add additional ABC9 timings
2020-07-23 11:57:07 +01:00
Miodrag Milanović
910f421324
Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic
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anlogic: Use dfflegalize.
2020-07-16 18:07:58 +02:00
Marcelina Kościelnicka
3050454d6e
anlogic: Use dfflegalize.
2020-07-14 05:02:50 +02:00
Lofty
a3a90f6377
Revert "intel_alm: direct M10K instantiation"
...
This reverts commit 09ecb9b2cf
.
2020-07-13 18:05:38 +02:00
Marcelina Kościelnicka
347dd01c2f
xilinx: Fix srl regression.
...
Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9. Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
2020-07-12 23:41:27 +02:00
Marcelina Kościelnicka
c73ebeb90e
gowin: Use dfflegalize.
2020-07-06 12:27:46 +02:00
Dan Ravensloft
09ecb9b2cf
intel_alm: direct M10K instantiation
2020-07-05 23:28:59 +02:00
Dan Ravensloft
7f45cab27a
synth_gowin: ABC9 support
...
This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
2020-07-05 22:07:17 +02:00
Dan Ravensloft
0d4c2f0a65
intel_alm: add Cyclone 10 GX tests
2020-07-05 21:36:38 +02:00
Dan Ravensloft
b004f09018
intel_alm: DSP inference
2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka
3ca2de0f77
synth_intel_alm: Use dfflegalize.
2020-07-04 22:56:16 +02:00
Dan Ravensloft
c6765443fd
Improve MISTRAL_FF specify rules
...
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2020-07-04 19:45:10 +02:00
Eddie Hung
52fbaeca07
tests: update fsm.ys resource count
...
Suspect it is to do with map/set ordering in techmap; should
be fixed by #1862 ?
2020-07-04 19:45:10 +02:00
Dan Ravensloft
8b4eb78849
intel_alm: fix DFFE matching
2020-06-11 19:55:51 +02:00
Claire Wolf
7112f187cd
Add missing .gitignore file
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 22:25:47 +02:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
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abc9: -dff improvements
2020-06-04 08:15:25 -07:00
Eddie Hung
45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
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abc9: fixes around handling combinatorial loops
2020-06-03 17:35:46 -07:00
Eddie Hung
8a11019d38
tests: tidy up testcase
2020-06-03 08:41:55 -07:00
Eddie Hung
46ed0db2ec
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings
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tests: reduce test warnings
2020-06-03 08:37:07 -07:00
Miodrag Milanovic
0a88f002e5
allow range for mux test
2020-06-01 13:48:19 +02:00
Eddie Hung
ea4374a223
abc9_ops: update messaging (credit to @Xiretza for spotting)
2020-05-30 08:57:48 -07:00
Eddie Hung
1dce798dc5
tests: add ecp5 latch testcase with -abc9
2020-05-25 16:39:16 -07:00
Eddie Hung
08221edbc1
tests: xilinx macc test to have initval, shorten BMC depth for runtime
2020-05-25 10:09:05 -07:00
Eddie Hung
60aa804915
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
Eddie Hung
9c6d216a06
tests: add test for abc9 -dff removing a redundant flop entirely
2020-05-25 08:43:33 -07:00
Eddie Hung
8dd93e389e
tests: add testcase for abc9 -dff preserving flop names
2020-05-25 08:43:33 -07:00
Marcelina Kościelnicka
aee439360b
Add force_downto and force_upto wire attributes.
...
Fixes #2058 .
2020-05-19 01:42:40 +02:00
Eddie Hung
7cd3f4a79b
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
...
Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
2020-05-14 10:33:56 -07:00
Eddie Hung
8d7b3c06b2
abc9: suppress warnings when no compatible + used flop boxes formed
2020-05-14 10:33:56 -07:00
Eddie Hung
cdd250ef16
xilinx: update abc9_dff tests
2020-05-14 10:33:56 -07:00
Eddie Hung
762b6ad74a
xilinx: remove no-longer-relevant test
2020-05-14 10:33:56 -07:00
Dan Ravensloft
5b779f7f4e
intel_alm: direct LUTRAM cell instantiation
...
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
Dan Ravensloft
3d149aff73
intel_alm: work around a Quartus ICE
2020-04-23 11:03:28 +02:00
Eddie Hung
988d47af85
tests: read +/xilinx/cell_sim.v before xilinx_dsp test
2020-04-22 17:50:30 -07:00
Eddie Hung
db09e96dff
test: ice40_dsp test to read +/ice40/cells_sim.v for default params
2020-04-22 16:35:35 -07:00
Eddie Hung
f582eb14af
xilinx: xilinx_dffopt to read cells_sim.v; fix test
2020-04-22 16:25:23 -07:00
Eddie Hung
38ee59184c
tests: remove write_ilang
2020-04-20 15:42:29 -07:00
Dan Ravensloft
2e37e62e6b
synth_intel_alm: alternative synthesis for Intel FPGAs
...
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00
whitequark
93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style
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ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
2020-04-10 14:51:01 +00:00
whitequark
763401fc82
ecp5: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
whitequark
ebee746ad2
ice40: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
Eddie Hung
4ae7f3a8ed
Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor
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opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
2020-04-01 14:17:01 -07:00
Eddie Hung
317c18fc6f
Simplify breaking tests/arch/*/fsm.ys tests
2020-03-20 11:25:17 -07:00
N. Engelhardt
644deb708d
fix argument order for macOS compatibility
2020-03-18 15:11:49 +01:00
Eddie Hung
3c2e910bb3
tests: extend tests/arch/run-tests.sh for defines
2020-03-05 08:08:32 -08:00
Claire Wolf
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
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Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
Eddie Hung
a179d918ec
Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"
...
This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
2020-02-27 10:17:29 -08:00
Eddie Hung
f858219c4e
Cleanup tests
2020-02-27 10:17:29 -08:00
Eddie Hung
717fb492b3
Update bug1630.ys to use -lut 4 instead of lut file
2020-02-27 10:17:29 -08:00
Eddie Hung
bc97e64b21
Fix tests/arch/xilinx/fsm.ys to count flops only
2020-02-27 10:17:29 -08:00
Alberto Gonzalez
f80fe8dc22
Change attribute search value to specify precise location instead of simple line number.
2020-02-24 02:41:08 +00:00
Marcin Kościelnicki
89adef352f
xilinx: Add support for LUT RAM on LUT4-based devices.
...
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.
Fixes #1549
2020-02-07 09:03:22 +01:00
Marcin Kościelnicki
d48950d92d
xilinx: Initial support for LUT4 devices.
...
Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.
Fixes #1547
2020-02-07 09:03:22 +01:00
whitequark
081d9318bc
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
...
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 16:52:51 +00:00
whitequark
3f4460a186
ice40: match memory inference attribute values case insensitive.
...
LSE/Synplify use case insensitive matching.
2020-02-06 14:58:20 +00:00
whitequark
fc28bf55aa
ice40: add support for both 1364.1 and LSE RAM/ROM attributes.
...
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify appear to interpret attribute values insensitive
to case. There is currently no way to do this in Yosys (attrmap
can only change case of attribute names).
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 14:58:20 +00:00
whitequark
29d130dee9
ice40: remove impossible test.
...
iCE40 does not have LUTRAM. This was erroneously added in commit
caab66111e
, and tested for BRAM,
essentially a duplicate of the "dpram.ys" test.
2020-02-06 14:58:20 +00:00
Eddie Hung
6eb7e925a1
Merge pull request #1650 from YosysHQ/eddie/shiftx2mux
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techmap LSB-first for compatible $shift/$shiftx cells
2020-02-05 14:55:57 -08:00
Eddie Hung
0b308c6835
abc9_ops: -reintegrate to use derived_type for box_ports
2020-02-05 14:46:48 -08:00
Eddie Hung
b6a1f627b5
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
2020-02-05 10:47:31 -08:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. ( #1673 )
2020-02-03 14:57:17 +01:00
Miodrag Milanović
71d148bcaa
Merge pull request #1559 from YosysHQ/efinix_test_fix
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Fix for non-deterministic test
2020-01-29 11:18:06 +01:00
Eddie Hung
7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
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Unpermute LUT ordering for ice40/ecp5/xilinx
2020-01-28 11:55:51 -08:00
Miodrag Milanovic
94191a93dd
Updated test to use assert-max
2020-01-28 18:26:10 +01:00
N. Engelhardt
086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
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synth_xilinx: error out if tristate without '-iopad'
2020-01-28 17:24:54 +01:00
Eddie Hung
cfb0366a18
Import tests from #1628
2020-01-27 13:56:16 -08:00
Eddie Hung
b178761551
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-24 11:59:48 -08:00
Eddie Hung
5aaa19f1ab
Update tests with reduced area
2020-01-21 16:50:04 -08:00
Eddie Hung
6a163b5ddd
xilinx_dsp: another typo; move xilinx specific test
2020-01-17 17:07:03 -08:00
Eddie Hung
db68e4c2a7
ice40_dsp: fix typo
2020-01-17 16:08:04 -08:00
Eddie Hung
5507c328ff
Add #1644 testcase
2020-01-17 15:57:52 -08:00
Eddie Hung
ad6c49fff1
ice40_dsp: add test
2020-01-17 15:38:26 -08:00
Eddie Hung
9fa0e03cc9
Merge pull request #1632 from YosysHQ/eddie/fix1630
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read_aiger: uniquify wires with $aiger<autoidx> prefix
2020-01-14 11:40:40 -08:00
Miodrag Milanović
9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr
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Export wire properties in EDIF
2020-01-14 19:19:32 +01:00
Eddie Hung
565d349dc9
Add #1630 testcase
2020-01-13 21:27:53 -08:00
Eddie Hung
ae619ba87a
Add #1626 testcase
2020-01-12 15:21:26 -08:00
Miodrag Milanovic
ccfe1e5909
this one is fine
2020-01-10 15:20:50 +01:00
Miodrag Milanovic
af852a0ea8
Fix tests
2020-01-10 14:48:01 +01:00
Eddie Hung
94ab3791ce
Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs
2020-01-07 15:44:18 -08:00
Eddie Hung
3df869cc7c
Add testcase from #1459
2020-01-06 16:22:22 -08:00
Eddie Hung
6e866030c2
Combine tests to check multiple clock domains
2020-01-02 14:38:59 -08:00
Eddie Hung
b454735bea
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-02 12:44:06 -08:00
Eddie Hung
9e5ff30d05
Merge pull request #1606 from YosysHQ/eddie/improve_tests
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Fix a few issues in tests/arch/*
2020-01-01 13:31:46 -08:00
Eddie Hung
52fe1e0c44
Revert insertion of 'reg', leave note behind
2020-01-01 09:05:46 -08:00
Miodrag Milanovic
a1344ec06e
Added a test case
2020-01-01 16:24:30 +01:00
Eddie Hung
713484fa66
Do not do call equiv_opt when no sim model exists
2019-12-31 18:40:30 -08:00
Eddie Hung
a59016b146
Fix warnings
2019-12-31 18:40:11 -08:00
Eddie Hung
c082329af3
Call equiv_opt with -multiclock and -assert
2019-12-31 18:39:32 -08:00
Eddie Hung
ccc0a740d2
Add some abc9 dff tests
2019-12-31 16:16:05 -08:00
Eddie Hung
0c4be94a02
Add -D DFF_MODE to abc9_map test
2019-12-30 20:13:25 -08:00
Eddie Hung
405e974fe5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 14:31:42 -08:00
Miodrag Milanović
c0a17c2457
Merge pull request #1589 from YosysHQ/iopad_default
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Make iopad option default for all xilinx flows
2019-12-30 20:34:31 +01:00
Eddie Hung
c2c74f9bb0
Merge pull request #1599 from YosysHQ/eddie/retry_1588
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Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
2019-12-30 10:01:02 -08:00
Miodrag Milanovic
f9749c202c
Fix new tests
2019-12-28 16:43:19 +01:00
Miodrag Milanovic
8c3de1d4bd
Merge remote-tracking branch 'origin/master' into iopad_default
2019-12-28 16:23:31 +01:00
Miodrag Milanovic
a82c701668
Make test without iopads
2019-12-28 16:22:24 +01:00
Miodrag Milanovic
509da7ed1a
Revert "Fix xilinx tests, when iopads are default"
...
This reverts commit 477e43d921
.
2019-12-28 16:12:45 +01:00
Eddie Hung
011f749ecf
Update resource count
2019-12-28 02:15:11 -08:00
Eddie Hung
d45869855c
Add #1598 testcase
2019-12-27 16:44:57 -08:00
Eddie Hung
2e21aa59a2
Add DSP cascade tests
2019-12-23 14:58:06 -08:00
Marcin Kościelnicki
666c6128a9
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
Miodrag Milanovic
436fea9e69
Addressed review comments
2019-12-21 20:23:23 +01:00
Miodrag Milanovic
477e43d921
Fix xilinx tests, when iopads are default
2019-12-21 13:18:44 +01:00
Eddie Hung
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
Marcin Kościelnicki
f382164d6e
tests/xilinx: fix flaky mux test
2019-12-18 15:53:29 +01:00
Marcin Kościelnicki
a235250403
xilinx: Add xilinx_dffopt pass ( #1557 )
2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
aff6ad1ce0
xilinx: Improve flip-flop handling.
...
This adds support for infering more kinds of flip-flops:
- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable
Some passes have been moved (and some added) in order for dff2dffs to
work correctly.
This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities). Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
2019-12-18 13:43:43 +01:00
Eddie Hung
a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
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xilinx: add LUTRAM rules for RAM32M, RAM64M
2019-12-16 21:48:21 -08:00
Eddie Hung
378d9e6e0c
Add another test
2019-12-16 13:57:55 -08:00
Eddie Hung
db0003410f
Accidentally commented out tests
2019-12-16 13:31:47 -08:00
Eddie Hung
5a00d5578c
Add unconditional match blocks for force RAM
2019-12-16 13:31:15 -08:00
Eddie Hung
e990c013c5
Merge blockram tests
2019-12-16 13:01:51 -08:00
Diego H
87e21b0122
Fixing compiler warning/issues. Moving test script to the correct place
2019-12-16 10:23:45 -06:00
Diego H
f3f59910eb
Removing fixed attribute value to !ramstyle rules
2019-12-15 23:51:58 -06:00
Diego H
b35559fc33
Merging attribute rules into a single match block; Adding tests
2019-12-15 23:33:09 -06:00
Eddie Hung
a5764a1236
Disable RAM16X1D test
2019-12-13 10:28:13 -08:00
Diego H
1c96345587
Renaming BRAM memory tests for the sake of uniformity
2019-12-13 09:33:18 -06:00
Eddie Hung
d0ee4cd88f
Remove extraneous synth_xilinx call
2019-12-12 19:00:26 -08:00
Eddie Hung
01116f0f0a
Add tests for these new models
2019-12-12 18:52:48 -08:00
Eddie Hung
037d1a03df
Add #1460 testcase
2019-12-12 17:49:55 -08:00
Eddie Hung
caab66111e
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
Diego H
751a18d7e9
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
2019-12-12 17:32:58 -06:00
Eddie Hung
bea15b537b
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-12 14:57:17 -08:00
Eddie Hung
47ac1b01e6
Add test
2019-12-12 14:43:13 -08:00
Diego H
e33f407655
Adding a note (TODO) in the memory_params.ys check file
2019-12-12 16:06:46 -06:00
Diego H
937ec1ee78
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
2019-12-12 13:50:36 -06:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
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Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
2019-12-09 17:38:48 -08:00
Eddie Hung
eff858cd33
unmap $__ICE40_CARRY_WRAPPER in test
2019-12-09 14:20:35 -08:00
Eddie Hung
e05372778a
ice40_wrapcarry to really preserve attributes via -unwrap option
2019-12-09 11:48:28 -08:00
Miodrag Milanovic
49c9b63e0f
Fix for non-deterministic test
2019-12-07 11:09:25 +01:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
946d5854c0
Drop keep=0 attributes on SB_CARRY
2019-12-06 17:27:47 -08:00
Jan Kowalewski
dcb30b5f4a
tests: arch: xilinx: Change order of arguments in macc.sh
2019-12-06 09:15:49 +01:00
Eddie Hung
d8fbf88980
Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER
2019-12-05 07:01:02 -08:00
Eddie Hung
19bc429482
abc9_map.v to transform INIT=1 to INIT=0
2019-12-04 21:36:41 -08:00
Eddie Hung
67f1ce2d43
Check SB_CARRY name also preserved
2019-12-03 14:51:39 -08:00
Eddie Hung
8de17877d4
Add testcase
2019-12-03 14:48:00 -08:00
Clifford Wolf
2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit
...
Gowin: add and test DFF init values
2019-12-03 08:43:18 -08:00
Pepijn de Vos
a7d34a7cb5
update test
2019-12-03 16:56:15 +01:00
Pepijn de Vos
a3b25b4af8
Use -match-init to not synth contradicting init values
2019-12-03 15:12:25 +01:00
Eddie Hung
de3476cc23
No need for -abc9
2019-11-26 23:08:14 -08:00
Eddie Hung
4a0198128e
Add citation
2019-11-26 22:51:16 -08:00
Eddie Hung
222e199b73
Add testcase derived from fastfir_dynamictaps benchmark
2019-11-26 21:26:30 -08:00