tangxifan
|
cfaae55bda
|
[lib] debugged fabric key assistant
|
2023-08-26 13:19:18 -07:00 |
|
tangxifan
|
adae7392e5
|
[lib] developing fabric key assistant
|
2023-08-26 12:54:12 -07:00 |
|
tangxifan
|
d3895c3dc0
|
[core] code format
|
2023-08-03 17:34:25 -07:00 |
|
tangxifan
|
53050b94ab
|
[core] developing memory group modules in grid modules
|
2023-08-01 17:50:03 -07:00 |
|
tangxifan
|
23643f3fb1
|
[core] developing the physical memory block builder
|
2023-07-31 22:57:26 -07:00 |
|
tangxifan
|
95a32628ab
|
[core] fixed the bug in arch bitgen due to the tile modules
|
2023-07-25 14:15:15 -07:00 |
|
tangxifan
|
7783229d90
|
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_fabric_tile
|
2023-07-23 20:44:50 -07:00 |
|
tangxifan
|
6607bb7e48
|
[core] now fpga verilog supports tile modules
|
2023-07-18 22:35:22 -07:00 |
Chung Shien Chai
|
b2f5b493c2
|
Fix the cpp-format
|
2023-07-16 13:08:40 -07:00 |
|
Chung Shien Chai
|
924622f5e5
|
Issue 1248 - fix bug bintoi_charvec()
|
2023-07-15 17:46:43 -07:00 |
|
tangxifan
|
091ac88c7e
|
[lib] code format
|
2023-07-14 12:16:40 -07:00 |
|
tangxifan
|
3bc959dcec
|
[lib] create tile config lib and start integration to core
|
2023-07-14 12:13:31 -07:00 |
|
tangxifan
|
d0831507c0
|
[lib] format fabric key writer
|
2023-07-06 19:21:45 -07:00 |
|
tangxifan
|
85f9899588
|
[lib] fixed some bugs and now fabric key io is working
|
2023-07-06 16:30:36 -07:00 |
|
tangxifan
|
74e776f3b0
|
[lib] syntax errors and now fabric key is under the namespace of openfpga
|
2023-07-06 11:57:22 -07:00 |
|
tangxifan
|
6c623d60f9
|
[lib] code format
|
2023-07-06 11:16:36 -07:00 |
|
tangxifan
|
82a60d64e3
|
[lib] add api to fabric key
|
2023-07-05 23:53:16 -07:00 |
|
tangxifan
|
ed25cf0dc4
|
[lib] developing sub key io and APIs
|
2023-07-05 21:18:33 -07:00 |
|
tangxifan
|
c2020d6cef
|
[lib] now use constants in xml io for fabric key
|
2023-07-04 21:04:21 -07:00 |
|
tangxifan
|
93158bdc62
|
[lib] adding subkey feature
|
2023-07-03 15:53:22 -07:00 |
|
tangxifan
|
1b9aeab2a7
|
[lib] reorganize the source files of libfabrickey
|
2023-07-03 15:02:23 -07:00 |
|
tangxifan
|
83fa6a421e
|
[core] code format
|
2023-06-26 10:06:17 -07:00 |
|
tangxifan
|
70f40cd21a
|
[core] fixing bugs in the preconfig module when supporting dut module of fpga_core
|
2023-06-26 10:03:19 -07:00 |
|
tangxifan
|
987a562e0f
|
[core] fixed the bug when checking mapping status of fpga core ports
|
2023-06-23 17:21:52 -07:00 |
|
tangxifan
|
b30148f8fb
|
[core] apply more sanity checks on top module port
|
2023-06-23 12:37:46 -07:00 |
|
tangxifan
|
d9f271eaed
|
[lib] fixed a bug where constant string is not initialized
|
2023-06-23 11:18:36 -07:00 |
|
tangxifan
|
8bd9ae02fd
|
[core] io name map now supports dummy port direction
|
2023-06-23 11:09:33 -07:00 |
|
tangxifan
|
0811409c4f
|
[lib] support dummy port direction in IoNameMap io
|
2023-06-22 23:20:22 -07:00 |
|
tangxifan
|
7961223eac
|
[core] enabling io naming rules in fabric builder
|
2023-06-22 22:18:09 -07:00 |
|
tangxifan
|
4d265c3965
|
[lib] reworked io name map data structure. Passed I/O test
|
2023-06-22 17:44:07 -07:00 |
|
tangxifan
|
a628a1e7b0
|
[lib] add missing file
|
2023-06-21 23:02:43 -07:00 |
|
tangxifan
|
b8d89d2a5c
|
[lib] code format
|
2023-06-21 22:51:38 -07:00 |
|
tangxifan
|
227d147dca
|
[lib] add an example file
|
2023-06-21 22:51:15 -07:00 |
|
tangxifan
|
77b082ab55
|
[src] debugging
|
2023-06-21 22:50:37 -07:00 |
|
tangxifan
|
f3c07d6138
|
[lib] finish the io for io naming rules
|
2023-06-21 21:48:52 -07:00 |
|
tangxifan
|
2ed86d1897
|
[lib] developing io for io naming rule
|
2023-06-21 18:08:45 -07:00 |
|
tangxifan
|
b42677aa9d
|
[lib] developing the io name mapping data structure
|
2023-06-21 17:33:40 -07:00 |
|
tangxifan
|
c7ade72200
|
[core] code complete for the core wrapper creator. Start debugging
|
2023-06-18 19:17:42 -07:00 |
|
tangxifan
|
e20ac5f272
|
[core] fixed a bug which cause configuration protocols other than ccff failed
|
2023-04-24 22:46:46 +08:00 |
|
tangxifan
|
18b078d1d5
|
[core] fixed bugs which cause ci failed
|
2023-04-24 21:20:07 +08:00 |
|
tangxifan
|
667d9df028
|
[core] developing testbench generator for ccff v2
|
2023-04-24 11:36:21 +08:00 |
|
tangxifan
|
ba90f5020b
|
[core] fixed some bugs which cause netlist generation failed
|
2023-04-23 16:48:14 +08:00 |
|
tangxifan
|
28b7a12f68
|
[core] code format
|
2023-04-23 14:31:35 +08:00 |
|
tangxifan
|
bd511ba515
|
[core] fixed syntax errors
|
2023-04-23 14:26:08 +08:00 |
|
tangxifan
|
592765af48
|
[core] code complete for upgrading netlist generator w.r.t. ccff v2
|
2023-04-23 13:57:37 +08:00 |
|
tangxifan
|
5500b9a289
|
[core] upgrading netlist generator
|
2023-04-22 16:27:27 +08:00 |
|
tangxifan
|
ea8ae29b53
|
[core] code format
|
2023-04-22 15:12:38 +08:00 |
|
tangxifan
|
297a23dee7
|
[core] fixed syntax errors
|
2023-04-22 15:09:39 +08:00 |
|
tangxifan
|
5e8e982334
|
[core] finished developing checkers
|
2023-04-22 12:44:34 +08:00 |
|
tangxifan
|
dba449f42a
|
[core] code complete for parsers
|
2023-04-21 23:45:35 +08:00 |
|
tangxifan
|
6e44f3f5fc
|
[core] developing ccff_v2 parsers
|
2023-04-21 17:01:51 +08:00 |
|
tangxifan
|
953625b1ca
|
[core] format
|
2023-03-05 22:32:05 -08:00 |
|
tangxifan
|
de1e300ec7
|
[core] now resize rr_node for clock graph is working
|
2023-03-05 22:21:55 -08:00 |
|
tangxifan
|
81e9187aac
|
[core] debugging
|
2023-03-03 22:55:14 -08:00 |
|
tangxifan
|
4423d917fa
|
[core] debugging
|
2023-03-03 18:00:43 -08:00 |
|
tangxifan
|
29ee6e7136
|
[core] debugging
|
2023-03-03 17:33:53 -08:00 |
|
tangxifan
|
98d8c75d86
|
[code] format
|
2023-03-02 21:36:08 -08:00 |
|
tangxifan
|
02b50e3464
|
[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
|
2023-03-02 21:33:32 -08:00 |
|
tangxifan
|
46510388be
|
[core] now fabric generator can wire clock ports to routing blocks
|
2023-03-02 12:33:26 -08:00 |
|
tangxifan
|
099d9f32f4
|
[core] dev
|
2023-03-01 16:08:15 -08:00 |
|
tangxifan
|
60ff298987
|
[lib] add new feature to enable clock tree connection to global ports of tiles
|
2023-02-28 22:36:41 -08:00 |
|
tangxifan
|
2ff8fb8737
|
[core] wrapping up clock routing command
|
2023-02-28 16:52:54 -08:00 |
|
tangxifan
|
8d5c21b14d
|
[core] code format
|
2023-02-27 23:00:15 -08:00 |
|
tangxifan
|
2735b708d3
|
[core] reworked the tapping XML syntax
|
2023-02-27 22:59:44 -08:00 |
|
tangxifan
|
ff69664c14
|
[core] syntax
|
2023-02-27 22:39:12 -08:00 |
|
tangxifan
|
d4e19edc71
|
[core] finishing up clock rr_graph appending
|
2023-02-27 22:31:16 -08:00 |
|
tangxifan
|
9f20d2e639
|
[lib] now clock arch supports tap points
|
2023-02-27 22:06:13 -08:00 |
|
tangxifan
|
3a40c5e15f
|
[lib] update example of clock arch definition
|
2023-02-27 21:49:14 -08:00 |
|
tangxifan
|
7d0c23c675
|
[lib] new api for lowest level clock connections
|
2023-02-27 15:16:23 -08:00 |
|
tangxifan
|
b3dec93eb9
|
[core] code format
|
2023-02-27 15:12:59 -08:00 |
|
tangxifan
|
9ec4d690db
|
[core] clock edges interconnecting clock tracks across levels
|
2023-02-27 15:10:36 -08:00 |
|
tangxifan
|
b6eace8fac
|
[core] now switch id is linked in clock network
|
2023-02-27 13:10:54 -08:00 |
|
tangxifan
|
009d711ba5
|
[core] code format
|
2023-02-26 22:23:41 -08:00 |
|
tangxifan
|
87a9146082
|
[core] adding rr spatial lookup for clock nodes only
|
2023-02-26 22:23:17 -08:00 |
|
tangxifan
|
db36f87dfa
|
[core] enhance clock tree arch validation
|
2023-02-26 18:39:53 -08:00 |
|
tangxifan
|
780fc0f26d
|
[core] developing validators and annotate rr_segment for clock arch
|
2023-02-26 18:03:55 -08:00 |
|
tangxifan
|
75773ddd4e
|
[code] format
|
2023-02-26 12:46:29 -08:00 |
|
tangxifan
|
3db5acfb37
|
[core] dev
|
2023-02-26 12:40:13 -08:00 |
|
tangxifan
|
8f0d94ba73
|
[code] format
|
2023-02-25 22:43:21 -08:00 |
|
tangxifan
|
0b33650761
|
[core] dev
|
2023-02-25 22:41:33 -08:00 |
|
tangxifan
|
7f07a9d031
|
[lib] add default seg/switch to clock arch. Fixed syntax
|
2023-02-24 19:15:39 -08:00 |
|
tangxifan
|
65b27a3377
|
[lib] fixed a few bugs
|
2023-02-22 21:29:18 -08:00 |
|
tangxifan
|
40f6b5a3fe
|
[lib] fixed a few bugs
|
2023-02-22 21:23:08 -08:00 |
|
tangxifan
|
a9d5e4dfbd
|
[lib] update example clock arch xml
|
2023-02-22 21:18:00 -08:00 |
|
tangxifan
|
d1133000ba
|
[lib] code format
|
2023-02-22 21:03:04 -08:00 |
|
tangxifan
|
aafd1e6fb3
|
[lib] syntax
|
2023-02-22 21:02:35 -08:00 |
|
tangxifan
|
b2ef1db5f4
|
[lib] finishing up code changes; start debugging
|
2023-02-22 20:46:18 -08:00 |
|
tangxifan
|
1c8a5eb098
|
[lib] adding linker
|
2023-02-22 20:29:32 -08:00 |
|
tangxifan
|
bf2876c60e
|
[lib] developing linker
|
2023-02-22 18:36:22 -08:00 |
|
tangxifan
|
ce20a16aad
|
[lib] adding unit test
|
2023-02-22 18:26:18 -08:00 |
|
tangxifan
|
b37deb4b02
|
[lib] adding writer
|
2023-02-22 18:21:28 -08:00 |
|
tangxifan
|
5cd310c4cc
|
[lib] adding missing apis
|
2023-02-22 15:04:52 -08:00 |
|
tangxifan
|
7bc843b74a
|
[lib] developing xml parser for clk arch
|
2023-02-22 13:23:09 -08:00 |
|
tangxifan
|
25e43b47da
|
[lib] first round of data structure on clock arch
|
2023-02-22 12:18:44 -08:00 |
|
tangxifan
|
9eb2374bc6
|
[lib] developing
|
2023-02-21 22:29:25 -08:00 |
|
tangxifan
|
fe594acab1
|
[lib] adding clock network data structure
|
2023-02-21 16:53:05 -08:00 |
|
tangxifan
|
e7fc065032
|
[lib] start developing clock arch data structure and I/O
|
2023-02-21 15:06:35 -08:00 |
|
tangxifan
|
ac8c0e243c
|
[core] code format
|
2023-01-15 12:13:59 -08:00 |
|
tangxifan
|
cab7e04901
|
[core] fixed a bug in repacker to avoid routing constrained nets
|
2023-01-15 12:13:12 -08:00 |
|
tangxifan
|
ff0a4dfccb
|
[lib] format
|
2023-01-08 22:41:07 -08:00 |