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[lib] add new feature to enable clock tree connection to global ports of tiles

This commit is contained in:
tangxifan 2023-02-28 22:36:41 -08:00
parent 5917446fbe
commit 60ff298987
4 changed files with 34 additions and 0 deletions
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8
libs/libarchopenfpga/src/read_xml_tile_annotation.cpp
View File

@ -89,6 +89,14 @@ static void read_xml_tile_global_port_annotation(
get_attribute(xml_tile, "is_clock", loc_data, pugiutil::ReqOpt::OPTIONAL)
.as_bool(false));
/* Get clock tree attributes if this is a clock */
if (tile_annotation.global_port_is_clock(tile_global_port_id)) {
tile_annotation.set_global_port_clock_arch_tree_name(
tile_global_port_id, get_attribute(xml_tile, "clock_arch_tree_name",
loc_data, pugiutil::ReqOpt::OPTIONAL)
.as_string());
}
/* Get is_set attributes */
tile_annotation.set_global_port_is_set(
tile_global_port_id,

13
libs/libarchopenfpga/src/tile_annotation.cpp
View File

@ -71,6 +71,12 @@ size_t TileAnnotation::global_port_default_value(
return global_port_default_values_[global_port_id];
}
std::string TileAnnotation::global_port_clock_arch_tree_name(
const TileGlobalPortId& global_port_id) const {
VTR_ASSERT(valid_global_port_id(global_port_id));
return global_port_clock_arch_tree_names_[global_port_id];
}
/************************************************************************
* Public Mutators
***********************************************************************/
@ -91,6 +97,7 @@ TileGlobalPortId TileAnnotation::create_global_port(
global_port_tile_ports_.emplace_back();
global_port_tile_coordinates_.emplace_back();
global_port_is_clock_.push_back(false);
global_port_clock_arch_tree_names_.emplace_back();
global_port_is_set_.push_back(false);
global_port_is_reset_.push_back(false);
global_port_default_values_.push_back(0);
@ -116,6 +123,12 @@ void TileAnnotation::set_global_port_is_clock(
global_port_is_clock_[global_port_id] = is_clock;
}
void TileAnnotation::set_global_port_clock_arch_tree_name(
const TileGlobalPortId& global_port_id, const std::string& clock_tree_name) {
VTR_ASSERT(valid_global_port_id(global_port_id));
global_port_clock_arch_tree_names_[global_port_id] = clock_tree_name;
}
void TileAnnotation::set_global_port_is_set(
const TileGlobalPortId& global_port_id, const bool& is_set) {
VTR_ASSERT(valid_global_port_id(global_port_id));

5
libs/libarchopenfpga/src/tile_annotation.h
View File

@ -51,6 +51,8 @@ class TileAnnotation {
bool global_port_is_clock(const TileGlobalPortId& global_port_id) const;
bool global_port_is_set(const TileGlobalPortId& global_port_id) const;
bool global_port_is_reset(const TileGlobalPortId& global_port_id) const;
std::string global_port_clock_arch_tree_name(
const TileGlobalPortId& global_port_id) const;
size_t global_port_default_value(
const TileGlobalPortId& global_port_id) const;
@ -66,6 +68,8 @@ class TileAnnotation {
const vtr::Point<size_t>& tile_coord);
void set_global_port_is_clock(const TileGlobalPortId& global_port_id,
const bool& is_clock);
void set_global_port_clock_arch_tree_name(
const TileGlobalPortId& global_port_id, const std::string& clock_tree_name);
void set_global_port_is_set(const TileGlobalPortId& global_port_id,
const bool& is_set);
void set_global_port_is_reset(const TileGlobalPortId& global_port_id,
@ -91,6 +95,7 @@ class TileAnnotation {
global_port_tile_coordinates_;
vtr::vector<TileGlobalPortId, std::vector<BasicPort>> global_port_tile_ports_;
vtr::vector<TileGlobalPortId, bool> global_port_is_clock_;
vtr::vector<TileGlobalPortId, std::string> global_port_clock_arch_tree_names_;
vtr::vector<TileGlobalPortId, bool> global_port_is_reset_;
vtr::vector<TileGlobalPortId, bool> global_port_is_set_;
vtr::vector<TileGlobalPortId, size_t> global_port_default_values_;

8
libs/libarchopenfpga/src/write_xml_tile_annotation.cpp
View File

@ -36,6 +36,14 @@ static void write_xml_tile_annotation_global_port(
write_xml_attribute(fp, "is_clock",
tile_annotation.global_port_is_clock(global_port_id));
if (tile_annotation.global_port_is_clock(global_port_id) &&
!tile_annotation.global_port_clock_arch_tree_name(global_port_id)
.empty()) {
write_xml_attribute(
fp, "clock_arch_tree_name",
tile_annotation.global_port_clock_arch_tree_name(global_port_id).c_str());
}
write_xml_attribute(fp, "is_set",
tile_annotation.global_port_is_set(global_port_id));