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[lib] syntax errors and now fabric key is under the namespace of openfpga

This commit is contained in:
tangxifan 2023-07-06 11:57:22 -07:00
parent 6c623d60f9
commit 74e776f3b0
9 changed files with 70 additions and 32 deletions
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19
libs/libfabrickey/src/base/fabric_key.cpp
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@ -5,6 +5,8 @@
#include "vtr_assert.h"
#include "vtr_log.h"
namespace openfpga { // Begin namespace openfpga
/************************************************************************
* Member functions for class FabricKey
***********************************************************************/
@ -44,13 +46,10 @@ FabricKey::fabric_key_module_range FabricKey::modules() const {
sub_key_module_ids_.end());
}
FabricKey::fabric_sub_key_range FabricKey::sub_keys(
std::vector<FabricSubKeyId> FabricKey::sub_keys(
const FabricKeyModuleId& module_id) const {
VTR_ASSERT(valid_module_id(module_id));
return vtr::make_range(
sub_key_ids_.begin() + size_t(module_sub_keys_[module_id][0]),
sub_key_ids_.begin() + size_t(module_sub_keys_[module_id][0]) +
size_t(module_sub_keys_[module_id].size() - 1));
return module_sub_keys_[module_id];
}
/************************************************************************
@ -277,6 +276,12 @@ void FabricKey::add_data_port_to_wl_shift_register_bank(
wl_bank_data_ports_[region_id][bank_id].push_back(data_port);
}
void FabricKey::reserve_modules(const size_t& num_modules) {
sub_key_module_ids_.reserve(num_modules);
sub_key_module_names_.reserve(num_modules);
module_sub_keys_.reserve(num_modules);
}
void FabricKey::reserve_module_keys(const FabricKeyModuleId& module_id,
const size_t& num_keys) {
VTR_ASSERT(valid_module_id(module_id));
@ -311,7 +316,7 @@ FabricSubKeyId FabricKey::create_module_key(
sub_key_values_.emplace_back();
sub_key_alias_.emplace_back();
/* Add the new id to module */
module_sub_keys_.emplace_back(key_id);
module_sub_keys_[module_id].emplace_back(key_id);
return key_id;
}
@ -377,3 +382,5 @@ bool FabricKey::valid_sub_key_id(const FabricSubKeyId& sub_key_id) const {
return (size_t(sub_key_id) < sub_key_ids_.size()) &&
(sub_key_id == sub_key_ids_[sub_key_id]);
}
} // End of namespace openfpga

26
libs/libfabrickey/src/base/fabric_key.h
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@ -16,6 +16,8 @@
#include "fabric_key_fwd.h"
#include "openfpga_port.h"
namespace openfpga { // Begin namespace openfpga
/********************************************************************
* A data structure to describe a secure key for fabric organization
* A fabric may consist of multiple regions
@ -69,7 +71,8 @@ class FabricKey {
fabric_bit_line_bank_range bl_banks(const FabricRegionId& region_id) const;
fabric_word_line_bank_range wl_banks(const FabricRegionId& region_id) const;
fabric_key_module_range modules() const;
fabric_sub_key_range sub_keys(const FabricKeyModuleId& module_id) const;
std::vector<FabricSubKeyId> sub_keys(
const FabricKeyModuleId& module_id) const;
public: /* Public Accessors: Basic data query */
/* Access all the keys of a region */
@ -92,12 +95,12 @@ class FabricKey {
/* Return a list of data ports which will be driven by a BL shift register
* bank */
std::vector<openfpga::BasicPort> bl_bank_data_ports(
std::vector<BasicPort> bl_bank_data_ports(
const FabricRegionId& region_id, const FabricBitLineBankId& bank_id) const;
/* Return a list of data ports which will be driven by a WL shift register
* bank */
std::vector<openfpga::BasicPort> wl_bank_data_ports(
std::vector<BasicPort> wl_bank_data_ports(
const FabricRegionId& region_id, const FabricWordLineBankId& bank_id) const;
public: /* Public Mutators: model-related */
@ -141,7 +144,7 @@ class FabricKey {
/* Add a data port to a given BL shift register bank */
void add_data_port_to_bl_shift_register_bank(
const FabricRegionId& region_id, const FabricBitLineBankId& bank_id,
const openfpga::BasicPort& data_port);
const BasicPort& data_port);
/* Create a new shift register bank for WLs and return an id */
FabricWordLineBankId create_wl_shift_register_bank(
@ -150,13 +153,14 @@ class FabricKey {
/* Add a data port to a given WL shift register bank */
void add_data_port_to_wl_shift_register_bank(
const FabricRegionId& region_id, const FabricWordLineBankId& bank_id,
const openfpga::BasicPort& data_port);
const BasicPort& data_port);
/* Reserve a number of keys to be memory efficent */
void reserve_modules(const size_t& num_modules);
void reserve_module_keys(const FabricKeyModuleId& module_id,
const size_t& num_keys);
/* Create a new key and add it to the library, return an id */
FabricModuleId create_module(const std::string& name);
FabricKeyModuleId create_module(const std::string& name);
FabricSubKeyId create_module_key(const FabricKeyModuleId& module_id);
/* Configure attributes of a sub key */
void set_sub_key_name(const FabricSubKeyId& key_id, const std::string& name);
@ -201,8 +205,8 @@ class FabricKey {
vtr::vector<FabricBitLineBankId, FabricBitLineBankId>>
bl_bank_ids_;
/* Data ports to be connected to each BL shift register bank */
vtr::vector<FabricRegionId, vtr::vector<FabricBitLineBankId,
std::vector<openfpga::BasicPort>>>
vtr::vector<FabricRegionId,
vtr::vector<FabricBitLineBankId, std::vector<BasicPort>>>
bl_bank_data_ports_;
/* Unique ids for each WL shift register bank */
@ -210,8 +214,8 @@ class FabricKey {
vtr::vector<FabricWordLineBankId, FabricWordLineBankId>>
wl_bank_ids_;
/* Data ports to be connected to each WL shift register bank */
vtr::vector<FabricRegionId, vtr::vector<FabricWordLineBankId,
std::vector<openfpga::BasicPort>>>
vtr::vector<FabricRegionId,
vtr::vector<FabricWordLineBankId, std::vector<BasicPort>>>
wl_bank_data_ports_;
/* ---- List of sub modules ---- */
@ -227,4 +231,6 @@ class FabricKey {
vtr::vector<FabricSubKeyId, std::string> sub_key_alias_;
};
} // End of namespace openfpga
#endif

4
libs/libfabrickey/src/base/fabric_key_fwd.h
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@ -12,6 +12,8 @@
#include "vtr_strong_id.h"
namespace openfpga { // Begin namespace openfpga
struct fabric_region_id_tag;
struct fabric_key_id_tag;
struct fabric_bit_line_bank_id_tag;
@ -29,4 +31,6 @@ typedef vtr::StrongId<fabric_key_module_id_tag> FabricKeyModuleId;
/* Short declaration of class */
class FabricKey;
} // End of namespace openfpga
#endif

4
libs/libfabrickey/src/io/fabric_key_xml_constants.h
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@ -1,6 +1,8 @@
#ifndef FABRIC_KEY_XML_CONSTANTS_H
#define FABRIC_KEY_XML_CONSTANTS_H
namespace openfpga { // Begin namespace openfpga
/* Constants required by XML parser */
constexpr const char* XML_FABRIC_KEY_ROOT_NAME = "fabric_key";
constexpr const char* XML_FABRIC_KEY_MODULE_NODE_NAME = "module";
@ -25,4 +27,6 @@ constexpr const char*
constexpr const char*
XML_FABRIC_KEY_BLWL_SHIFT_REGISTER_BANK_ATTRIBUTE_RANGE_NAME = "range";
} // End of namespace openfpga
#endif

31
libs/libfabrickey/src/io/read_xml_fabric_key.cpp
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@ -24,6 +24,8 @@
#include "read_xml_fabric_key.h"
#include "read_xml_util.h"
namespace openfpga { // Begin namespace openfpga
/********************************************************************
* Parse XML codes of a <key> to an object of FabricKey
*******************************************************************/
@ -32,10 +34,9 @@ static void read_xml_module_key(pugi::xml_node& xml_component_key,
FabricKey& fabric_key,
const FabricKeyModuleId& module_id) {
/* Find the id of component key */
const size_t& id =
get_attribute(xml_component_key, XML_FABRIC_KEY_KEY_ATTRIBUTE_ID_NAME,
loc_data)
.as_int();
size_t id = get_attribute(xml_component_key,
XML_FABRIC_KEY_KEY_ATTRIBUTE_ID_NAME, loc_data)
.as_int();
FabricSubKeyId sub_key_id = fabric_key.sub_keys(module_id)[id];
@ -325,7 +326,7 @@ static void read_xml_fabric_key_top_module(pugi::xml_node& xml_module,
const pugiutil::loc_data& loc_data,
FabricKey& fabric_key) {
size_t num_regions =
std::distance(xml_root.children().begin(), xml_root.children().end());
std::distance(xml_module.children().begin(), xml_module.children().end());
/* Reserve memory space for the region */
fabric_key.reserve_regions(num_regions);
for (size_t iregion = 0; iregion < num_regions; ++iregion) {
@ -335,10 +336,10 @@ static void read_xml_fabric_key_top_module(pugi::xml_node& xml_module,
/* Reserve memory space for the keys */
size_t num_keys = 0;
for (pugi::xml_node xml_region : xml_root.children()) {
for (pugi::xml_node xml_region : xml_module.children()) {
/* Error out if the XML child has an invalid name! */
if (xml_region.name() != std::string(XML_FABRIC_KEY_REGION_NODE_NAME)) {
bad_tag(xml_region, loc_data, xml_root,
bad_tag(xml_region, loc_data, xml_module,
{XML_FABRIC_KEY_REGION_NODE_NAME});
}
num_keys +=
@ -353,10 +354,10 @@ static void read_xml_fabric_key_top_module(pugi::xml_node& xml_module,
/* Iterate over the children under this node,
* each child should be named after circuit_model
*/
for (pugi::xml_node xml_region : xml_root.children()) {
for (pugi::xml_node xml_region : xml_module.children()) {
/* Error out if the XML child has an invalid name! */
if (xml_region.name() != std::string(XML_FABRIC_KEY_REGION_NODE_NAME)) {
bad_tag(xml_region, loc_data, xml_root,
bad_tag(xml_region, loc_data, xml_module,
{XML_FABRIC_KEY_REGION_NODE_NAME});
}
read_xml_fabric_region(xml_region, loc_data, fabric_key);
@ -400,14 +401,14 @@ static void read_xml_fabric_key_module(pugi::xml_node& xml_module,
*parser
* - For regular module, we follow regular parser
*******************************************************************/
static void read_xml_fabric_key_by_modules(pugi::xml_node& xml_module,
const pugiutil::loc_data& loc_data,
FabricKey& fabric_key) {
static void read_xml_fabric_keys_by_modules(pugi::xml_node& xml_module,
const pugiutil::loc_data& loc_data,
FabricKey& fabric_key) {
std::string name =
get_attribute(xml_module, XML_FABRIC_KEY_MODULE_ATTRIBUTE_NAME_NAME,
loc_data)
.as_string();
if (name == std::string(FPGA_TOP_MODULE_NAME)) {
if (name == std::string(openfpga::FPGA_TOP_MODULE_NAME)) {
read_xml_fabric_key_top_module(xml_module, loc_data, fabric_key);
} else {
read_xml_fabric_key_module(xml_module, loc_data, fabric_key);
@ -447,7 +448,7 @@ FabricKey read_xml_fabric_key(const char* key_fname) {
{XML_FABRIC_KEY_MODULE_NODE_NAME});
}
/* Parse fabric keys by module */
read_xml_fabric_keys_by_module(xml_module, loc_data, fabric_key);
read_xml_fabric_keys_by_modules(xml_module, loc_data, fabric_key);
}
} catch (pugiutil::XmlError& e) {
@ -456,3 +457,5 @@ FabricKey read_xml_fabric_key(const char* key_fname) {
return fabric_key;
}
} // End of namespace openfpga

5
libs/libfabrickey/src/io/read_xml_fabric_key.h
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@ -9,6 +9,11 @@
/********************************************************************
* Function declaration
*******************************************************************/
namespace openfpga { // Begin namespace openfpga
FabricKey read_xml_fabric_key(const char* key_fname);
} // End of namespace openfpga
#endif

4
libs/libfabrickey/src/io/write_xml_fabric_key.cpp
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@ -21,6 +21,8 @@
#include "fabric_key_xml_constants.h"
#include "write_xml_fabric_key.h"
namespace openfpga { // Begin namespace openfpga
/********************************************************************
* A writer to output a component key to XML format
*
@ -238,3 +240,5 @@ int write_xml_fabric_key(const char* fname, const FabricKey& fabric_key) {
return err_code;
}
} // End of namespace openfpga

5
libs/libfabrickey/src/io/write_xml_fabric_key.h
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@ -11,6 +11,11 @@
/********************************************************************
* Function declaration
*******************************************************************/
namespace openfpga { // Begin namespace openfpga
int write_xml_fabric_key(const char* fname, const FabricKey& fabric_key);
} // End of namespace openfpga
#endif

4
libs/libfabrickey/test/test_fabric_key.cpp
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@ -16,14 +16,14 @@ int main(int argc, const char** argv) {
VTR_ASSERT((2 == argc) || (3 == argc));
/* Parse the fabric key from an XML file */
FabricKey test_key = read_xml_fabric_key(argv[1]);
openfpga::FabricKey test_key = openfpga::read_xml_fabric_key(argv[1]);
VTR_LOG("Read the fabric key from an XML file: %s.\n", argv[1]);
/* Output the circuit library to an XML file
* This is optional only used when there is a second argument
*/
if (3 <= argc) {
write_xml_fabric_key(argv[2], test_key);
openfpga::write_xml_fabric_key(argv[2], test_key);
VTR_LOG("Echo the fabric key to an XML file: %s.\n", argv[2]);
}
}