[lib] finish the io for io naming rules

libs/libionamemap/src/base/io_name_map.cpp

@@ -17,6 +17,17 @@ namespace openfpga {
 /**************************************************
  * Public Accessors
  *************************************************/
+std::vector<BasicPort> IoNameMap::fpga_top_ports() const {
+  std::vector<BasicPort> ports;
+
+  for (auto it = top2core_io_name_map_.begin();
+       it != top2core_io_name_map_.end(); ++it) {
+    ports.push_back(it->first);
+  }
+
+  return ports;
+}
+
 BasicPort IoNameMap::fpga_core_port(const BasicPort& fpga_top_port) const {
   BasicPort core_port;
   auto result = top2core_io_name_map_.find(fpga_top_port);
@@ -35,6 +46,10 @@ BasicPort IoNameMap::fpga_top_port(const BasicPort& fpga_core_port) const {
   return top_port;
 }
 
+bool IoNameMap::fpga_top_port_is_dummy(const BasicPort& fpga_top_port) const {
+  return !fpga_core_port(fpga_top_port).is_valid();
+}
+
 int IoNameMap::set_io_pair(const BasicPort& fpga_top_port,
                            const BasicPort& fpga_core_port) {
   /* Ensure the two ports are matching in size */

libs/libionamemap/src/base/io_name_map.h

@@ -20,12 +20,16 @@ namespace openfpga {
  */
 class IoNameMap {
  public: /* Public accessors */
+  /** @brief Get all the fpga top ports */
+  std::vector<BasicPort> fpga_top_ports() const;
   /** @brief With a given port at fpga_top, find the corresponding I/O at
    * fpga_core. Return an invalid port if not found */
   BasicPort fpga_core_port(const BasicPort& fpga_top_port) const;
   /** @brief With a given port at fpga_core, find the corresponding I/O at
    * fpga_top. Return an invalid port if not found */
   BasicPort fpga_top_port(const BasicPort& fpga_core_port) const;
+  /** @brief Identify if the fpga_top port is dummy or not */
+  bool fpga_top_port_is_dummy(const BasicPort& fpga_top_port) const;
 
  public: /* Public mutators */
   /** @brief Create the one-on-one mapping between an port of fpga_top and

libs/libionamemap/src/io/write_xml_io_name_map.cpp

@@ -0,0 +1,102 @@
+/********************************************************************
+ * This file includes functions that outputs a clock network object to XML
+ *format
+ *******************************************************************/
+/* Headers from system goes first */
+#include <algorithm>
+#include <string>
+
+/* Headers from vtr util library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from openfpga util library */
+#include "openfpga_digest.h"
+
+/* Headers from arch openfpga library */
+#include "write_xml_utils.h"
+
+/* Headers from pin constraint library */
+#include "io_name_map_xml_constants.h"
+#include "write_xml_io_name_map.h"
+
+namespace openfpga {  // Begin namespace openfpga
+
+/********************************************************************
+ * A writer to output a I/O name mapping to XML format
+ *
+ * Return 0 if successful
+ * Return 1 if there are more serious bugs in the architecture
+ * Return 2 if fail when creating files
+ *******************************************************************/
+static int write_xml_io_map_port(std::fstream& fp, const IoNameMap& io_name_map,
+                                 const BasicPort& fpga_top_port) {
+  /* Validate the file stream */
+  if (false == openfpga::valid_file_stream(fp)) {
+    return 2;
+  }
+
+  openfpga::write_tab_to_file(fp, 1);
+  fp << "<" << XML_IO_NAME_MAP_NODE_NAME << "";
+  write_xml_attribute(fp, XML_IO_NAME_MAP_ATTRIBUTE_TOP_NAME,
+                      generate_xml_port_name(fpga_top_port).c_str());
+
+  if (io_name_map.fpga_top_port_is_dummy(fpga_top_port)) {
+    write_xml_attribute(fp, XML_IO_NAME_MAP_ATTRIBUTE_IS_DUMMY, "true");
+  } else {
+    BasicPort fpga_core_port = io_name_map.fpga_core_port(fpga_top_port);
+    write_xml_attribute(fp, XML_IO_NAME_MAP_ATTRIBUTE_CORE_NAME,
+                        generate_xml_port_name(fpga_core_port).c_str());
+  }
+  fp << ">"
+     << "\n";
+
+  return 0;
+}
+
+/********************************************************************
+ * A writer to output an object to XML format
+ *
+ * Return 0 if successful
+ * Return 1 if there are more serious bugs in the architecture
+ * Return 2 if fail when creating files
+ *******************************************************************/
+int write_xml_io_name_map(const char* fname, const IoNameMap& io_name_map) {
+  vtr::ScopedStartFinishTimer timer("Write I/O naming rules");
+
+  /* Create a file handler */
+  std::fstream fp;
+  /* Open the file stream */
+  fp.open(std::string(fname), std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  openfpga::check_file_stream(fname, fp);
+
+  /* Write the root node */
+  fp << "<" << XML_IO_NAME_MAP_ROOT_NAME;
+  fp << ">"
+     << "\n";
+
+  int err_code = 0;
+
+  /* Write each port */
+  for (BasicPort fpga_top_port : io_name_map.fpga_top_ports()) {
+    /* Write bus */
+    err_code = write_xml_io_map_port(fp, io_name_map, fpga_top_port);
+    if (0 != err_code) {
+      return err_code;
+    }
+  }
+
+  /* Finish writing the root node */
+  fp << "</" << XML_IO_NAME_MAP_ROOT_NAME << ">"
+     << "\n";
+
+  /* Close the file stream */
+  fp.close();
+
+  return err_code;
+}
+
+}  // End of namespace openfpga

libs/libionamemap/src/io/write_xml_io_name_map.h

@@ -0,0 +1,20 @@
+#ifndef WRITE_XML_IO_NAME_MAP_H
+#define WRITE_XML_IO_NAME_MAP_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+
+#include "io_name_map.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+namespace openfpga {  // Begin namespace openfpga
+
+int write_xml_io_name_map(const char* fname, const IoNameMap& io_name_map);
+
+}  // End of namespace openfpga
+
+#endif