[lib] finish the io for io naming rules
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@ -17,6 +17,17 @@ namespace openfpga {
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/**************************************************
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* Public Accessors
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*************************************************/
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std::vector<BasicPort> IoNameMap::fpga_top_ports() const {
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std::vector<BasicPort> ports;
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for (auto it = top2core_io_name_map_.begin();
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it != top2core_io_name_map_.end(); ++it) {
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ports.push_back(it->first);
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}
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return ports;
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}
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BasicPort IoNameMap::fpga_core_port(const BasicPort& fpga_top_port) const {
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BasicPort core_port;
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auto result = top2core_io_name_map_.find(fpga_top_port);
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@ -35,6 +46,10 @@ BasicPort IoNameMap::fpga_top_port(const BasicPort& fpga_core_port) const {
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return top_port;
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}
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bool IoNameMap::fpga_top_port_is_dummy(const BasicPort& fpga_top_port) const {
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return !fpga_core_port(fpga_top_port).is_valid();
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}
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int IoNameMap::set_io_pair(const BasicPort& fpga_top_port,
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const BasicPort& fpga_core_port) {
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/* Ensure the two ports are matching in size */
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@ -20,12 +20,16 @@ namespace openfpga {
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*/
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class IoNameMap {
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public: /* Public accessors */
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/** @brief Get all the fpga top ports */
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std::vector<BasicPort> fpga_top_ports() const;
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/** @brief With a given port at fpga_top, find the corresponding I/O at
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* fpga_core. Return an invalid port if not found */
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BasicPort fpga_core_port(const BasicPort& fpga_top_port) const;
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/** @brief With a given port at fpga_core, find the corresponding I/O at
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* fpga_top. Return an invalid port if not found */
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BasicPort fpga_top_port(const BasicPort& fpga_core_port) const;
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/** @brief Identify if the fpga_top port is dummy or not */
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bool fpga_top_port_is_dummy(const BasicPort& fpga_top_port) const;
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public: /* Public mutators */
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/** @brief Create the one-on-one mapping between an port of fpga_top and
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@ -0,0 +1,102 @@
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/********************************************************************
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* This file includes functions that outputs a clock network object to XML
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*format
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*******************************************************************/
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/* Headers from system goes first */
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#include <algorithm>
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#include <string>
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/* Headers from vtr util library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "vtr_time.h"
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/* Headers from openfpga util library */
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#include "openfpga_digest.h"
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/* Headers from arch openfpga library */
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#include "write_xml_utils.h"
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/* Headers from pin constraint library */
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#include "io_name_map_xml_constants.h"
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#include "write_xml_io_name_map.h"
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namespace openfpga { // Begin namespace openfpga
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/********************************************************************
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* A writer to output a I/O name mapping to XML format
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*
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* Return 0 if successful
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* Return 1 if there are more serious bugs in the architecture
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* Return 2 if fail when creating files
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*******************************************************************/
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static int write_xml_io_map_port(std::fstream& fp, const IoNameMap& io_name_map,
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const BasicPort& fpga_top_port) {
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/* Validate the file stream */
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if (false == openfpga::valid_file_stream(fp)) {
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return 2;
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}
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openfpga::write_tab_to_file(fp, 1);
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fp << "<" << XML_IO_NAME_MAP_NODE_NAME << "";
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write_xml_attribute(fp, XML_IO_NAME_MAP_ATTRIBUTE_TOP_NAME,
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generate_xml_port_name(fpga_top_port).c_str());
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if (io_name_map.fpga_top_port_is_dummy(fpga_top_port)) {
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write_xml_attribute(fp, XML_IO_NAME_MAP_ATTRIBUTE_IS_DUMMY, "true");
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} else {
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BasicPort fpga_core_port = io_name_map.fpga_core_port(fpga_top_port);
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write_xml_attribute(fp, XML_IO_NAME_MAP_ATTRIBUTE_CORE_NAME,
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generate_xml_port_name(fpga_core_port).c_str());
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}
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fp << ">"
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<< "\n";
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return 0;
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}
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/********************************************************************
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* A writer to output an object to XML format
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*
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* Return 0 if successful
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* Return 1 if there are more serious bugs in the architecture
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* Return 2 if fail when creating files
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*******************************************************************/
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int write_xml_io_name_map(const char* fname, const IoNameMap& io_name_map) {
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vtr::ScopedStartFinishTimer timer("Write I/O naming rules");
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/* Create a file handler */
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std::fstream fp;
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/* Open the file stream */
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fp.open(std::string(fname), std::fstream::out | std::fstream::trunc);
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/* Validate the file stream */
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openfpga::check_file_stream(fname, fp);
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/* Write the root node */
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fp << "<" << XML_IO_NAME_MAP_ROOT_NAME;
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fp << ">"
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<< "\n";
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int err_code = 0;
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/* Write each port */
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for (BasicPort fpga_top_port : io_name_map.fpga_top_ports()) {
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/* Write bus */
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err_code = write_xml_io_map_port(fp, io_name_map, fpga_top_port);
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if (0 != err_code) {
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return err_code;
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}
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}
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/* Finish writing the root node */
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fp << "</" << XML_IO_NAME_MAP_ROOT_NAME << ">"
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<< "\n";
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/* Close the file stream */
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fp.close();
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return err_code;
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}
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} // End of namespace openfpga
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@ -0,0 +1,20 @@
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#ifndef WRITE_XML_IO_NAME_MAP_H
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#define WRITE_XML_IO_NAME_MAP_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <fstream>
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#include "io_name_map.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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namespace openfpga { // Begin namespace openfpga
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int write_xml_io_name_map(const char* fname, const IoNameMap& io_name_map);
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} // End of namespace openfpga
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#endif
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