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[lib] fixed some bugs and now fabric key io is working

This commit is contained in:
tangxifan 2023-07-06 16:30:36 -07:00
parent 74e776f3b0
commit 85f9899588
3 changed files with 163 additions and 33 deletions
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25
libs/libfabrickey/src/base/fabric_key.cpp
View File

@ -100,6 +100,29 @@ std::vector<openfpga::BasicPort> FabricKey::wl_bank_data_ports(
return wl_bank_data_ports_[region_id][bank_id];
}
std::string FabricKey::module_name(const FabricKeyModuleId& module_id) const {
VTR_ASSERT(valid_module_id(module_id));
return sub_key_module_names_[module_id];
}
std::string FabricKey::sub_key_name(const FabricSubKeyId& key_id) const {
/* validate the key_id */
VTR_ASSERT(valid_sub_key_id(key_id));
return sub_key_names_[key_id];
}
size_t FabricKey::sub_key_value(const FabricSubKeyId& key_id) const {
/* validate the key_id */
VTR_ASSERT(valid_sub_key_id(key_id));
return sub_key_values_[key_id];
}
std::string FabricKey::sub_key_alias(const FabricSubKeyId& key_id) const {
/* validate the key_id */
VTR_ASSERT(valid_sub_key_id(key_id));
return sub_key_alias_[key_id];
}
/************************************************************************
* Public Mutators
***********************************************************************/
@ -300,6 +323,7 @@ FabricKeyModuleId FabricKey::create_module(const std::string& name) {
}
/* Create a new id */
FabricKeyModuleId module_id = FabricKeyModuleId(sub_key_module_ids_.size());
sub_key_module_ids_.push_back(module_id);
sub_key_module_names_.push_back(name);
module_sub_keys_.emplace_back();
/* Register in lookup */
@ -312,6 +336,7 @@ FabricSubKeyId FabricKey::create_module_key(
VTR_ASSERT(valid_module_id(module_id));
/* Create a new id */
FabricSubKeyId key_id = FabricSubKeyId(sub_key_ids_.size());
sub_key_ids_.push_back(key_id);
sub_key_names_.emplace_back();
sub_key_values_.emplace_back();
sub_key_alias_.emplace_back();

9
libs/libfabrickey/src/base/fabric_key.h
View File

@ -77,16 +77,12 @@ class FabricKey {
public: /* Public Accessors: Basic data query */
/* Access all the keys of a region */
std::vector<FabricKeyId> region_keys(const FabricRegionId& region_id) const;
/* Access the name of a key */
std::string key_name(const FabricKeyId& key_id) const;
/* Access the value of a key */
size_t key_value(const FabricKeyId& key_id) const;
/* Access the alias of a key */
std::string key_alias(const FabricKeyId& key_id) const;
/* Access the coordinate of a key */
vtr::Point<int> key_coordinate(const FabricKeyId& key_id) const;
@ -103,6 +99,11 @@ class FabricKey {
std::vector<BasicPort> wl_bank_data_ports(
const FabricRegionId& region_id, const FabricWordLineBankId& bank_id) const;
std::string module_name(const FabricKeyModuleId& module_id) const;
std::string sub_key_name(const FabricSubKeyId& key_id) const;
size_t sub_key_value(const FabricSubKeyId& key_id) const;
std::string sub_key_alias(const FabricSubKeyId& key_id) const;
public: /* Public Mutators: model-related */
/* Reserve a number of regions to be memory efficent */
void reserve_regions(const size_t& num_regions);

162
libs/libfabrickey/src/io/write_xml_fabric_key.cpp
View File

@ -13,6 +13,7 @@
/* Headers from openfpga util library */
#include "openfpga_digest.h"
#include "openfpga_reserved_words.h"
/* Headers from arch openfpga library */
#include "write_xml_utils.h"
@ -23,6 +24,48 @@
namespace openfpga { // Begin namespace openfpga
/********************************************************************
* A writer to output a component sub key to XML format
*
* Return 0 if successful
* Return 1 if there are more serious bugs in the architecture
* Return 2 if fail when creating files
*******************************************************************/
static int write_xml_fabric_component_sub_key(
std::fstream& fp, const FabricKey& fabric_key,
const FabricSubKeyId& component_key, const size_t& key_idx,
const size_t& level) {
/* Validate the file stream */
if (false == openfpga::valid_file_stream(fp)) {
return 2;
}
openfpga::write_tab_to_file(fp, level);
fp << "<" << XML_FABRIC_KEY_KEY_NODE_NAME;
if (false == fabric_key.valid_sub_key_id(component_key)) {
return 1;
}
write_xml_attribute(fp, XML_FABRIC_KEY_KEY_ATTRIBUTE_ID_NAME, key_idx);
if (!fabric_key.sub_key_name(component_key).empty()) {
write_xml_attribute(fp, XML_FABRIC_KEY_KEY_ATTRIBUTE_NAME_NAME,
fabric_key.sub_key_name(component_key).c_str());
}
write_xml_attribute(fp, XML_FABRIC_KEY_KEY_ATTRIBUTE_VALUE_NAME,
fabric_key.sub_key_value(component_key));
if (!fabric_key.sub_key_alias(component_key).empty()) {
write_xml_attribute(fp, XML_FABRIC_KEY_KEY_ATTRIBUTE_ALIAS_NAME,
fabric_key.sub_key_alias(component_key).c_str());
}
fp << "/>"
<< "\n";
return 0;
}
/********************************************************************
* A writer to output a component key to XML format
*
@ -80,7 +123,8 @@ static int write_xml_fabric_component_key(std::fstream& fp,
* Return 2 if fail when creating files
*******************************************************************/
static int write_xml_fabric_bl_shift_register_banks(
std::fstream& fp, const FabricKey& fabric_key, const FabricRegionId& region) {
std::fstream& fp, const FabricKey& fabric_key, const FabricRegionId& region,
const size_t& level) {
/* Validate the file stream */
if (false == openfpga::valid_file_stream(fp)) {
return 2;
@ -92,12 +136,12 @@ static int write_xml_fabric_bl_shift_register_banks(
}
/* Write the root node */
openfpga::write_tab_to_file(fp, 2);
openfpga::write_tab_to_file(fp, level);
fp << "<" << XML_FABRIC_KEY_BL_SHIFT_REGISTER_BANKS_NODE_NAME << ">"
<< "\n";
for (const auto& bank : fabric_key.bl_banks(region)) {
openfpga::write_tab_to_file(fp, 3);
openfpga::write_tab_to_file(fp, level + 1);
fp << "<" << XML_FABRIC_KEY_BLWL_SHIFT_REGISTER_BANK_NODE_NAME;
write_xml_attribute(
@ -120,7 +164,7 @@ static int write_xml_fabric_bl_shift_register_banks(
<< "\n";
}
openfpga::write_tab_to_file(fp, 2);
openfpga::write_tab_to_file(fp, level);
fp << "</" << XML_FABRIC_KEY_BL_SHIFT_REGISTER_BANKS_NODE_NAME << ">"
<< "\n";
@ -135,7 +179,8 @@ static int write_xml_fabric_bl_shift_register_banks(
* Return 2 if fail when creating files
*******************************************************************/
static int write_xml_fabric_wl_shift_register_banks(
std::fstream& fp, const FabricKey& fabric_key, const FabricRegionId& region) {
std::fstream& fp, const FabricKey& fabric_key, const FabricRegionId& region,
const size_t& level) {
/* Validate the file stream */
if (false == openfpga::valid_file_stream(fp)) {
return 2;
@ -147,12 +192,12 @@ static int write_xml_fabric_wl_shift_register_banks(
}
/* Write the root node */
openfpga::write_tab_to_file(fp, 2);
openfpga::write_tab_to_file(fp, level);
fp << "<" << XML_FABRIC_KEY_WL_SHIFT_REGISTER_BANKS_NODE_NAME << ">"
<< "\n";
for (const auto& bank : fabric_key.wl_banks(region)) {
openfpga::write_tab_to_file(fp, 3);
openfpga::write_tab_to_file(fp, level + 1);
fp << "<" << XML_FABRIC_KEY_BLWL_SHIFT_REGISTER_BANK_NODE_NAME;
write_xml_attribute(
@ -175,13 +220,83 @@ static int write_xml_fabric_wl_shift_register_banks(
<< "\n";
}
openfpga::write_tab_to_file(fp, 2);
openfpga::write_tab_to_file(fp, level);
fp << "</" << XML_FABRIC_KEY_WL_SHIFT_REGISTER_BANKS_NODE_NAME << ">"
<< "\n";
return 0;
}
/* Write keys under the top-level module to a file */
static int write_xml_top_module_keys(std::fstream& fp,
const FabricKey& fabric_key,
const size_t& level) {
int err_code = 0;
/* Write the module declaration */
openfpga::write_tab_to_file(fp, level);
fp << "<" << XML_FABRIC_KEY_MODULE_NODE_NAME << " "
<< XML_FABRIC_KEY_MODULE_ATTRIBUTE_NAME_NAME << "=\""
<< FPGA_TOP_MODULE_NAME << "\""
<< ">\n";
/* Write region by region */
for (const FabricRegionId& region : fabric_key.regions()) {
openfpga::write_tab_to_file(fp, level + 1);
fp << "<" << XML_FABRIC_KEY_REGION_NODE_NAME << " "
<< XML_FABRIC_KEY_REGION_ATTRIBUTE_ID_NAME << "=\"" << size_t(region)
<< "\""
<< ">\n";
/* Write shift register banks */
write_xml_fabric_bl_shift_register_banks(fp, fabric_key, region, level + 2);
write_xml_fabric_wl_shift_register_banks(fp, fabric_key, region, level + 2);
/* Write component by component */
for (const FabricKeyId& key : fabric_key.region_keys(region)) {
err_code = write_xml_fabric_component_key(fp, fabric_key, key);
if (0 != err_code) {
return err_code;
}
}
openfpga::write_tab_to_file(fp, level + 1);
fp << "</" << XML_FABRIC_KEY_REGION_NODE_NAME << ">"
<< "\n";
}
fp << "</" << XML_FABRIC_KEY_MODULE_NODE_NAME << ">\n";
return err_code;
}
/* Write keys under the a given module to a file */
static int write_xml_module_keys(std::fstream& fp, const FabricKey& fabric_key,
const FabricKeyModuleId& module_id,
const size_t& level) {
int err_code = 0;
/* Write the module declaration */
openfpga::write_tab_to_file(fp, level);
fp << "<" << XML_FABRIC_KEY_MODULE_NODE_NAME << " "
<< XML_FABRIC_KEY_MODULE_ATTRIBUTE_NAME_NAME << "=\""
<< fabric_key.module_name(module_id) << "\""
<< ">\n";
/* Write component by component */
size_t key_idx = 0;
for (const FabricSubKeyId& key : fabric_key.sub_keys(module_id)) {
err_code = write_xml_fabric_component_sub_key(fp, fabric_key, key, key_idx,
level + 1);
if (0 != err_code) {
return err_code;
}
key_idx++;
}
fp << "</" << XML_FABRIC_KEY_MODULE_NODE_NAME << ">\n";
return err_code;
}
/********************************************************************
* A writer to output a fabric key to XML format
*
@ -206,29 +321,18 @@ int write_xml_fabric_key(const char* fname, const FabricKey& fabric_key) {
int err_code = 0;
/* Write region by region */
for (const FabricRegionId& region : fabric_key.regions()) {
openfpga::write_tab_to_file(fp, 1);
fp << "<" << XML_FABRIC_KEY_REGION_NODE_NAME << " "
<< XML_FABRIC_KEY_REGION_ATTRIBUTE_ID_NAME << "=\"" << size_t(region)
<< "\""
<< ">\n";
/* Write the top-level module */
err_code = write_xml_top_module_keys(fp, fabric_key, 1);
if (0 != err_code) {
return err_code;
}
/* Write shift register banks */
write_xml_fabric_bl_shift_register_banks(fp, fabric_key, region);
write_xml_fabric_wl_shift_register_banks(fp, fabric_key, region);
/* Write component by component */
for (const FabricKeyId& key : fabric_key.region_keys(region)) {
err_code = write_xml_fabric_component_key(fp, fabric_key, key);
if (0 != err_code) {
return err_code;
}
/* Write regular modules */
for (FabricKeyModuleId module_id : fabric_key.modules()) {
err_code = write_xml_module_keys(fp, fabric_key, module_id, 1);
if (0 != err_code) {
return err_code;
}
openfpga::write_tab_to_file(fp, 1);
fp << "</" << XML_FABRIC_KEY_REGION_NODE_NAME << ">"
<< "\n";
}
/* Finish writing the root node */