riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[src] debugging

This commit is contained in:
tangxifan 2023-06-21 22:50:37 -07:00
parent f3c07d6138
commit 77b082ab55
2 changed files with 41 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
libs/libionamemap/src/io/read_xml_io_name_map.cpp
View File

@ -39,8 +39,8 @@ static int read_xml_io_map_port(pugi::xml_node& xml_port,
/* For dummy port, create the dummy io */
bool is_dummy =
get_attribute(xml_port, XML_IO_NAME_MAP_ATTRIBUTE_IS_DUMMY, loc_data)
.as_bool();
get_attribute(xml_port, XML_IO_NAME_MAP_ATTRIBUTE_IS_DUMMY, loc_data, pugiutil::ReqOpt::OPTIONAL)
.as_bool(false);
if (is_dummy) {
return io_name_map.set_dummy_io(top_port); /* Early return */
}
@ -55,7 +55,7 @@ static int read_xml_io_map_port(pugi::xml_node& xml_port,
}
/********************************************************************
* Parse XML codes about <clock_network> to an object of ClockNetwork
* Parse XML codes about <ports> to an object of ClockNetwork
*******************************************************************/
int read_xml_io_name_map(const char* fname, IoNameMap& io_name_map) {
vtr::ScopedStartFinishTimer timer("Read I/O naming rules");

38
libs/libionamemap/test/xml_io_io_name_map.cpp Normal file
View File

@ -0,0 +1,38 @@
/********************************************************************
* Unit test functions to validate the correctness of
* 1. parser of data structures
* 2. writer of data structures
*******************************************************************/
/* Headers from vtrutils */
#include "vtr_assert.h"
#include "vtr_log.h"
/* Headers from readarchopenfpga */
#include "read_xml_io_name_map.h"
#include "write_xml_io_name_map.h"
int main(int argc, const char** argv) {
/* Ensure we have only one or two argument */
VTR_ASSERT((2 == argc) || (3 == argc));
int status = 0;
/* Parse the circuit library from an XML file */
openfpga::IoNameMap io_name_map;
status = openfpga::read_xml_io_name_map(argv[1], io_name_map);
if (status != 0) {
return status;
}
VTR_LOG("Parsed %lu fpga top ports from XML.\n",
io_name_map.fpga_top_ports().size());
/* Output the bus group to an XML file
* This is optional only used when there is a second argument
*/
if (3 <= argc) {
status = openfpga::write_xml_io_name_map(argv[2], io_name_map);
VTR_LOG("Write the I/O name mapping to an XML file: %s.\n", argv[2]);
}
return status;
}