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[lib] syntax

This commit is contained in:
tangxifan 2023-02-22 21:02:35 -08:00
parent b2ef1db5f4
commit aafd1e6fb3
6 changed files with 14 additions and 14 deletions
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2
libs/libclkarchopenfpga/CMakeLists.txt
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@ -20,8 +20,8 @@ set_target_properties(libclkarchopenfpga PROPERTIES PREFIX "") #Avoid extra 'lib
#Specify link-time dependancies
target_link_libraries(libclkarchopenfpga
libopenfpgautil
libarchopenfpga
libvtrutil
libarchfpga
libpugiutil)
#Create the test executable

12
libs/libclkarchopenfpga/src/base/clock_network.cpp
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@ -93,7 +93,7 @@ vtr::Point<int> ClockNetwork::spine_switch_point(const ClockSpineId& spine_id, c
return spine_switch_coords_[spine_id][size_t(switch_point_id)];
}
bool ClockNetwork::find_spine(const std::string& name) const {
ClockSpineId ClockNetwork::find_spine(const std::string& name) const {
auto result = spine_name2id_map_.find(name);
if (result == spine_name2id_map_.end()) {
return ClockSpineId::INVALID();
@ -128,7 +128,7 @@ void ClockNetwork::reserve_trees(const size_t& num_trees) {
tree_top_spines_.reserve(num_trees);
}
ClockTreeId ClockNetwork::create_tree(const std::string& name, const size_t& width = 1) {
ClockTreeId ClockNetwork::create_tree(const std::string& name, size_t width) {
/* Create a new id */
ClockTreeId tree_id = ClockTreeId(tree_ids_.size());
@ -208,7 +208,7 @@ void ClockNetwork::set_spine_end_point(const ClockSpineId& spine_id, const vtr::
void ClockNetwork::add_spine_switch_point(const ClockSpineId& spine_id, const ClockSpineId& drive_spine_id, const vtr::Point<int>& coord) {
VTR_ASSERT(valid_spine_id(spine_id));
VTR_ASSERT(valid_spine_id(drive_spine_id));
spine_switch_points_[spine_id].push_back(drive_spine);
spine_switch_points_[spine_id].push_back(drive_spine_id);
spine_switch_coords_[spine_id].push_back(coord);
/* Do not allow any spine has different parents */
if (spine_parents_[drive_spine_id]) {
@ -225,7 +225,7 @@ void ClockNetwork::add_spine_switch_point(const ClockSpineId& spine_id, const Cl
bool ClockNetwork::link() {
is_dirty_ = true;
for (ClockTreeId& tree_id : trees()) {
for (ClockTreeId tree_id : trees()) {
if (!link_tree(tree_id)) {
return false;
}
@ -277,7 +277,7 @@ bool ClockNetwork::rec_update_spine_level(const ClockSpineId& spine_id) {
bool ClockNetwork::update_tree_depth(const ClockTreeId& tree_id) {
size_t depth = 0;
for (ClockSpineId spine_id : tree_spines_[tree_id]) {
for (ClockSpineId spine_id : spines(tree_id)) {
depth = std::max(depth, spine_levels_[spine_id]);
}
tree_depths_[tree_id] = depth;
@ -295,7 +295,7 @@ bool ClockNetwork::valid_spine_id(const ClockSpineId& spine_id) const {
return (size_t(spine_id) < spine_ids_.size()) && (spine_id == spine_ids_[spine_id]);
}
bool valid_spine_switch_point_id(const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) const {
bool ClockNetwork::valid_spine_switch_point_id(const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) const {
if (!valid_spine_id(spine_id)) {
return false;
}

2
libs/libclkarchopenfpga/src/base/clock_network.h
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@ -73,7 +73,7 @@ class ClockNetwork {
/* Reserve a number of trees to be memory efficent */
void reserve_trees(const size_t& num_trees);
/* Create a new tree, by default the tree can accomodate only 1 clock signal; use width to adjust the size */
ClockTreeId create_tree(const std::string& name, const size_t& width = 1);
ClockTreeId create_tree(const std::string& name, size_t width = 1);
/* Create a new spine, if the spine is already created, return an invalid id */
ClockSpineId create_spine(const std::string& name);
/* Try to create a new spine, if the spine is already existing, return the id. If not, create a new spine and return its id */

4
libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp
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@ -167,8 +167,8 @@ ClockNetwork read_xml_clock_network(const char* fname) {
for (pugi::xml_node xml_tree : xml_root.children()) {
/* Error out if the XML child has an invalid name! */
if (xml_tree.name() != std::string(XML_CLOCK_NETWORK_NODE_NAME)) {
bad_tag(xml_tree, loc_data, xml_root, {XML_CLOCK_NETWORK_NODE_NAME});
if (xml_tree.name() != std::string(XML_CLOCK_TREE_NODE_NAME)) {
bad_tag(xml_tree, loc_data, xml_root, {XML_CLOCK_TREE_NODE_NAME});
}
read_xml_clock_tree(xml_tree, loc_data, clk_ntwk);
}

6
libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp
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@ -28,8 +28,8 @@ static int write_xml_clock_spine_switch_point(std::fstream& fp, const ClockNetwo
fp << "<" << XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME << "";
write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_TAP,
clk_ntwk.spine_switch_point_tap(spine_id, switch_point_id));
vtr::Point<int> coord = clk_ntwk.spine_switch_point(spine_id);
clk_ntwk.spine_name(clk_ntwk.spine_switch_point_tap(spine_id, switch_point_id)).c_str());
vtr::Point<int> coord = clk_ntwk.spine_switch_point(spine_id, switch_point_id);
write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_X,
coord.x());
write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y,
@ -47,7 +47,7 @@ static int write_xml_clock_spine(std::fstream& fp, const ClockNetwork& clk_ntwk,
fp << "<" << XML_CLOCK_SPINE_NODE_NAME << "";
write_xml_attribute(fp, XML_CLOCK_SPINE_ATTRIBUTE_NAME,
clk_ntwk.spine_name(spine_id));
clk_ntwk.spine_name(spine_id).c_str());
vtr::Point<int> start_coord = clk_ntwk.spine_start_point(spine_id);
write_xml_attribute(fp, XML_CLOCK_SPINE_ATTRIBUTE_START_X,
start_coord.x());

2
libs/libclkarchopenfpga/test/xml_io_clock_network.cpp
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@ -16,7 +16,7 @@ int main(int argc, const char** argv) {
VTR_ASSERT((2 == argc) || (3 == argc));
/* Parse the circuit library from an XML file */
const openfpga::ClockNetwork& clk_ntwk = openfpga::read_xml_clock_network(argv[1]);
openfpga::ClockNetwork clk_ntwk = openfpga::read_xml_clock_network(argv[1]);
VTR_LOG("Parsed %lu clock tree(s) from XML into clock network.\n",
clk_ntwk.trees().size());