[lib] support dummy port direction in IoNameMap io
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7961223eac
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0811409c4f
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@ -258,4 +258,20 @@ BasicPort IoNameMap::str2port(const std::string& port_str) const {
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return PortParser(port_str).port();
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}
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IoNameMap::e_dummy_port_direction IoNameMap::str2dummy_port_dir(const std::string& dir_str, const bool& verbose) const {
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for (int itype = IoNameMap::e_dummy_port_direction::INPUT; itype != IoNameMap::e_dummy_direction::NUM_TYPES; ++itype) {
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if (dir_str == std::string(DUMMY_PORT_DIR_STRING_[itype])) {
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return static_case<IoNameMap::e_dummy_port_direction>(itype);
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}
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}
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std::string full_types = "[";
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for (int itype = IoNameMap::e_dummy_port_direction::INPUT; itype != IoNameMap::e_dummy_direction::NUM_TYPES; ++itype) {
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full_types += std::string(DUMMY_PORT_DIR_STRING_[itype]) + std::string("|");
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}
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full_types.pop_back();
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full_types += "]";
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VTR_LOGV_ERROR(verbose, "Invalid direction for dummy port! Expect %s\n", full_types.c_str());
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return IoNameMap::e_dummy_port_direction::NUM_TYPES;
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}
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} /* end namespace openfpga */
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@ -21,7 +21,7 @@ namespace openfpga {
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class IoNameMap {
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public: /* Types */
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enum class e_dummy_port_direction {
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INPUT,
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INPUT = 0,
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OUTPUT,
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INOUT,
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NUM_TYPES
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@ -51,6 +51,10 @@ class IoNameMap {
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* fpga_core */
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int set_dummy_io(const BasicPort& fpga_top_port, const e_dummy_port_direction& direction);
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public: /* Public utility */
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/** @brief Parse the dummy port direction from string to valid type. Parser error can be turned on */
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e_dummy_port_direction str2dummy_port_dir(const std::string& dir_str, const bool& verbose = false) const;
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private: /* Internal utility */
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/* Convert a port info to string, which can be used to store keys */
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std::string port2str(const BasicPort& port) const;
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@ -70,6 +74,9 @@ class IoNameMap {
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std::map<std::string, BasicPort> core2top_io_name_map_;
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std::map<std::string, e_dummy_port_direction> dummy_port_direction_;
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/* Constants */
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std::array<const char*, e_dummy_port_direction::NUM_TYPES> DUMMY_PORT_DIR_STRING_;
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};
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} /* End namespace openfpga*/
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@ -45,12 +45,12 @@ static int read_xml_io_map_port(pugi::xml_node& xml_port,
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std::string dir_str =
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get_attribute(xml_port, XML_IO_NAME_MAP_ATTRIBUTE_DIRECTION, loc_data)
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.as_string();
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for (auto acceptable_dir_str : XML_IO_NAME_MAP_DUMMY_PORT_DIRECTION_STRING) {
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if (dir_str == std::string(acceptable_dir_str)) {
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}
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IoNameMap::e_dummy_port_direction dummy_port_dir = io_name_map.str2dummy_port_dir(dir_str, true);
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if (!io_name_map.valid_dummy_port_direction(dummy_port_dir)) {
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VTR_LOG_ERROR("Invalid direction for dummy port '%s'!\n", top_port.to_verilog_string().c_str());
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return CMD_EXEC_FATAL_ERROR;
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}
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return io_name_map.set_dummy_io(top_port); /* Early return */
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return io_name_map.set_dummy_io(top_port, dummy_port_dir); /* Early return */
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}
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/* This is not a dummy io, create the io mapping */
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