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[lib] support dummy port direction in IoNameMap io

This commit is contained in:
tangxifan 2023-06-22 23:20:22 -07:00
parent 7961223eac
commit 0811409c4f
3 changed files with 29 additions and 6 deletions
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16
libs/libionamemap/src/base/io_name_map.cpp
View File

@ -258,4 +258,20 @@ BasicPort IoNameMap::str2port(const std::string& port_str) const {
return PortParser(port_str).port();
}
IoNameMap::e_dummy_port_direction IoNameMap::str2dummy_port_dir(const std::string& dir_str, const bool& verbose) const {
for (int itype = IoNameMap::e_dummy_port_direction::INPUT; itype != IoNameMap::e_dummy_direction::NUM_TYPES; ++itype) {
if (dir_str == std::string(DUMMY_PORT_DIR_STRING_[itype])) {
return static_case<IoNameMap::e_dummy_port_direction>(itype);
}
}
std::string full_types = "[";
for (int itype = IoNameMap::e_dummy_port_direction::INPUT; itype != IoNameMap::e_dummy_direction::NUM_TYPES; ++itype) {
full_types += std::string(DUMMY_PORT_DIR_STRING_[itype]) + std::string("|");
}
full_types.pop_back();
full_types += "]";
VTR_LOGV_ERROR(verbose, "Invalid direction for dummy port! Expect %s\n", full_types.c_str());
return IoNameMap::e_dummy_port_direction::NUM_TYPES;
}
} /* end namespace openfpga */

9
libs/libionamemap/src/base/io_name_map.h
View File

@ -21,7 +21,7 @@ namespace openfpga {
class IoNameMap {
public: /* Types */
enum class e_dummy_port_direction {
INPUT,
INPUT = 0,
OUTPUT,
INOUT,
NUM_TYPES
@ -51,6 +51,10 @@ class IoNameMap {
* fpga_core */
int set_dummy_io(const BasicPort& fpga_top_port, const e_dummy_port_direction& direction);
public: /* Public utility */
/** @brief Parse the dummy port direction from string to valid type. Parser error can be turned on */
e_dummy_port_direction str2dummy_port_dir(const std::string& dir_str, const bool& verbose = false) const;
private: /* Internal utility */
/* Convert a port info to string, which can be used to store keys */
std::string port2str(const BasicPort& port) const;
@ -70,6 +74,9 @@ class IoNameMap {
std::map<std::string, BasicPort> core2top_io_name_map_;
std::map<std::string, e_dummy_port_direction> dummy_port_direction_;
/* Constants */
std::array<const char*, e_dummy_port_direction::NUM_TYPES> DUMMY_PORT_DIR_STRING_;
};
} /* End namespace openfpga*/

10
libs/libionamemap/src/io/read_xml_io_name_map.cpp
View File

@ -45,12 +45,12 @@ static int read_xml_io_map_port(pugi::xml_node& xml_port,
std::string dir_str =
get_attribute(xml_port, XML_IO_NAME_MAP_ATTRIBUTE_DIRECTION, loc_data)
.as_string();
for (auto acceptable_dir_str : XML_IO_NAME_MAP_DUMMY_PORT_DIRECTION_STRING) {
if (dir_str == std::string(acceptable_dir_str)) {
}
IoNameMap::e_dummy_port_direction dummy_port_dir = io_name_map.str2dummy_port_dir(dir_str, true);
if (!io_name_map.valid_dummy_port_direction(dummy_port_dir)) {
VTR_LOG_ERROR("Invalid direction for dummy port '%s'!\n", top_port.to_verilog_string().c_str());
return CMD_EXEC_FATAL_ERROR;
}
return io_name_map.set_dummy_io(top_port); /* Early return */
return io_name_map.set_dummy_io(top_port, dummy_port_dir); /* Early return */
}
/* This is not a dummy io, create the io mapping */