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[core] code format

This commit is contained in:
tangxifan 2023-04-22 15:12:38 +08:00
parent 297a23dee7
commit ea8ae29b53
10 changed files with 128 additions and 79 deletions
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57
libs/libarchopenfpga/src/config_protocol.cpp
View File

@ -1,6 +1,6 @@
#include "openfpga_tokenizer.h"
#include "config_protocol.h"
#include "openfpga_tokenizer.h"
#include "vtr_assert.h"
#include "vtr_log.h"
@ -11,9 +11,7 @@
/************************************************************************
* Constructors
***********************************************************************/
ConfigProtocol::ConfigProtocol() {
INDICE_STRING_DELIM_ = ',';
}
ConfigProtocol::ConfigProtocol() { INDICE_STRING_DELIM_ = ','; }
/************************************************************************
* Public Accessors
@ -36,7 +34,8 @@ std::vector<openfpga::BasicPort> ConfigProtocol::prog_clock_ports() const {
return keys;
}
std::string ConfigProtocol::prog_clock_port_ccff_head_indices_str(const openfpga::BasicPort& port) const {
std::string ConfigProtocol::prog_clock_port_ccff_head_indices_str(
const openfpga::BasicPort& port) const {
std::string ret("");
std::vector<size_t> raw = prog_clock_port_ccff_head_indices(port);
if (!raw.empty()) {
@ -50,7 +49,8 @@ std::string ConfigProtocol::prog_clock_port_ccff_head_indices_str(const openfpga
return ret;
}
std::vector<size_t> ConfigProtocol::prog_clock_port_ccff_head_indices(const openfpga::BasicPort& port) const {
std::vector<size_t> ConfigProtocol::prog_clock_port_ccff_head_indices(
const openfpga::BasicPort& port) const {
std::vector<size_t> ret;
auto result = prog_clk_ccff_head_indices_.find(port);
if (result != prog_clk_ccff_head_indices_.end()) {
@ -107,7 +107,8 @@ void ConfigProtocol::set_num_regions(const int& num_regions) {
num_regions_ = num_regions;
}
void ConfigProtocol::set_prog_clock_port_ccff_head_indices_pair(const openfpga::BasicPort& port, const std::string& indices_str) {
void ConfigProtocol::set_prog_clock_port_ccff_head_indices_pair(
const openfpga::BasicPort& port, const std::string& indices_str) {
openfpga::StringToken tokenizer(indices_str);
std::vector<size_t> token_int;
token_int.reserve(tokenizer.split(INDICE_STRING_DELIM_).size());
@ -116,7 +117,11 @@ void ConfigProtocol::set_prog_clock_port_ccff_head_indices_pair(const openfpga::
}
auto result = prog_clk_ccff_head_indices_.find(port);
if (result != prog_clk_ccff_head_indices_.end()) {
VTR_LOG_WARN("Overwrite the pair between programming clock port '%s[%d:%d]' and ccff head indices (previous: '%s', current: '%s')!\n", port.get_name().c_str(), port.get_lsb(), port.get_msb(), prog_clock_port_ccff_head_indices_str(port).c_str(), indices_str.c_str());
VTR_LOG_WARN(
"Overwrite the pair between programming clock port '%s[%d:%d]' and ccff "
"head indices (previous: '%s', current: '%s')!\n",
port.get_name().c_str(), port.get_lsb(), port.get_msb(),
prog_clock_port_ccff_head_indices_str(port).c_str(), indices_str.c_str());
}
prog_clk_ccff_head_indices_[port] = token_int;
}
@ -211,40 +216,55 @@ int ConfigProtocol::validate_ccff_prog_clocks() const {
/* Initialize scoreboard */
std::vector<int> ccff_head_scoreboard(num_regions(), 0);
for (openfpga::BasicPort port : prog_clock_ports()) {
/* Must be valid first */
/* Must be valid first */
if (port.is_valid()) {
VTR_LOG_ERROR("Programming clock '%s[%d:%d]' is not a valid port!\n", port.get_name().c_str(), port.get_lsb(), port.get_msb());
VTR_LOG_ERROR("Programming clock '%s[%d:%d]' is not a valid port!\n",
port.get_name().c_str(), port.get_lsb(), port.get_msb());
num_err++;
}
/* Each port should have a width of 1 */
/* Each port should have a width of 1 */
if (port.get_width() != 1) {
VTR_LOG_ERROR("Expect each programming clock has a size of 1 in the definition. '%s[%d:%d]' violates the rule!\n", port.get_name().c_str(), port.get_lsb(), port.get_msb());
VTR_LOG_ERROR(
"Expect each programming clock has a size of 1 in the definition. "
"'%s[%d:%d]' violates the rule!\n",
port.get_name().c_str(), port.get_lsb(), port.get_msb());
num_err++;
}
/* Fill scoreboard */
for (size_t ccff_head_idx : prog_clock_port_ccff_head_indices(port)) {
if (ccff_head_idx >= ccff_head_scoreboard.size()) {
VTR_LOG_ERROR("Programming clock '%s[%d:%d]' controlls an invalid ccff head '%ld' (Expect [0, '%ld'])!\n", port.get_name().c_str(), port.get_lsb(), port.get_msb(), ccff_head_idx, ccff_head_scoreboard.size() - 1);
VTR_LOG_ERROR(
"Programming clock '%s[%d:%d]' controlls an invalid ccff head '%ld' "
"(Expect [0, '%ld'])!\n",
port.get_name().c_str(), port.get_lsb(), port.get_msb(),
ccff_head_idx, ccff_head_scoreboard.size() - 1);
num_err++;
}
ccff_head_scoreboard[ccff_head_idx]++;
}
}
if (prog_clock_ports().size() != (size_t)num_regions()) {
VTR_LOG_ERROR("Number of programming clocks '%ld' does not match the number of configuration regions '%ld'!\n", prog_clock_ports().size(), num_regions());
VTR_LOG_ERROR(
"Number of programming clocks '%ld' does not match the number of "
"configuration regions '%ld'!\n",
prog_clock_ports().size(), num_regions());
num_err++;
}
for (size_t iregion = 0; iregion < ccff_head_scoreboard.size(); iregion++) {
if (ccff_head_scoreboard[iregion] == 0) {
VTR_LOG_ERROR("Configuration chain '%ld' is not driven by any programming clock!\n", iregion);
VTR_LOG_ERROR(
"Configuration chain '%ld' is not driven by any programming clock!\n",
iregion);
num_err++;
}
if (ccff_head_scoreboard[iregion] > 1) {
VTR_LOG_ERROR("Configuration chain '%ld' is driven by %ld programming clock!\n", iregion, ccff_head_scoreboard[iregion]);
VTR_LOG_ERROR(
"Configuration chain '%ld' is driven by %ld programming clock!\n",
iregion, ccff_head_scoreboard[iregion]);
num_err++;
}
}
return num_err;
return num_err;
}
/************************************************************************
@ -255,6 +275,5 @@ int ConfigProtocol::validate() const {
if (type() == CONFIG_MEM_SCAN_CHAIN) {
num_err += validate_ccff_prog_clocks();
}
return num_err;
return num_err;
}

31
libs/libarchopenfpga/src/config_protocol.h
View File

@ -1,8 +1,8 @@
#ifndef CONFIG_PROTOCOL_H
#define CONFIG_PROTOCOL_H
#include <string>
#include <map>
#include <string>
#include "circuit_library_fwd.h"
#include "circuit_types.h"
@ -30,12 +30,14 @@ class ConfigProtocol {
std::string memory_model_name() const;
CircuitModelId memory_model() const;
int num_regions() const;
/* Get a list of programming clock ports */
std::vector<openfpga::BasicPort> prog_clock_ports() const;
/* Get a list of programming clock ports */
std::string prog_clock_port_ccff_head_indices_str(const openfpga::BasicPort& port) const;
std::vector<size_t> prog_clock_port_ccff_head_indices(const openfpga::BasicPort& port) const;
std::string prog_clock_port_ccff_head_indices_str(
const openfpga::BasicPort& port) const;
std::vector<size_t> prog_clock_port_ccff_head_indices(
const openfpga::BasicPort& port) const;
e_blwl_protocol_type bl_protocol_type() const;
std::string bl_memory_model_name() const;
@ -45,14 +47,17 @@ class ConfigProtocol {
std::string wl_memory_model_name() const;
CircuitModelId wl_memory_model() const;
size_t wl_num_banks() const;
public: /* Public Mutators */
void set_type(const e_config_protocol_type& type);
void set_memory_model_name(const std::string& memory_model_name);
void set_memory_model(const CircuitModelId& memory_model);
void set_num_regions(const int& num_regions);
/* Add a pair of programming clock port and ccff head indices. This API will parse the index list, e.g., "0,1" to a vector of integers [0 1] */
void set_prog_clock_port_ccff_head_indices_pair(const openfpga::BasicPort& port, const std::string& indices_str);
/* Add a pair of programming clock port and ccff head indices. This API will
* parse the index list, e.g., "0,1" to a vector of integers [0 1] */
void set_prog_clock_port_ccff_head_indices_pair(
const openfpga::BasicPort& port, const std::string& indices_str);
void set_bl_protocol_type(const e_blwl_protocol_type& type);
void set_bl_memory_model_name(const std::string& memory_model_name);
@ -64,13 +69,15 @@ class ConfigProtocol {
void set_wl_num_banks(const size_t& num_banks);
public: /* Public validators */
/* Check if internal data has any conflicts to each other. Return number of errors detected */
/* Check if internal data has any conflicts to each other. Return number of
* errors detected */
int validate() const;
private: /* Private validators */
/* For configuration chains, to validate if
/* For configuration chains, to validate if
* - programming clocks is smaller than the number of regions
* - programming clocks does not have any conflicts in controlling regions (no overlaps)
* - programming clocks does not have any conflicts in controlling regions (no
* overlaps)
* - each region has been assigned to a programming clock
* Return number of errors detected
*/
@ -90,8 +97,10 @@ class ConfigProtocol {
/* Number of configurable regions */
int num_regions_;
/* Programming clock managment: This is only applicable to configuration chain protocols */
std::map<openfpga::BasicPort, std::vector<size_t>> prog_clk_ccff_head_indices_;
/* Programming clock managment: This is only applicable to configuration chain
* protocols */
std::map<openfpga::BasicPort, std::vector<size_t>>
prog_clk_ccff_head_indices_;
char INDICE_STRING_DELIM_;
/* BL & WL protocol: This is only applicable to memory-bank configuration

8
libs/libarchopenfpga/src/config_protocol_xml_constants.h
View File

@ -2,9 +2,11 @@
#define CONFIG_PROTOCOL_XML_CONSTANTS_H
/* Constants for XML parsers, including readers and writers */
constexpr const char* XML_CONFIG_PROTOCOL_NUM_REGIONS_ATTR = "num_regions";
constexpr const char* XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME = "programming_clock";
constexpr const char* XML_CONFIG_PROTOCOL_NUM_REGIONS_ATTR = "num_regions";
constexpr const char* XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME =
"programming_clock";
constexpr const char* XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR = "port";
constexpr const char* XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR = "ccff_head_indices";
constexpr const char* XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR =
"ccff_head_indices";
#endif

29
libs/libarchopenfpga/src/read_xml_config_protocol.cpp
View File

@ -15,8 +15,8 @@
/* Headers from libarchfpga */
#include "arch_error.h"
#include "config_protocol_xml_constants.h"
#include "read_xml_config_protocol.h"
#include "openfpga_port_parser.h"
#include "read_xml_config_protocol.h"
#include "read_xml_util.h"
/********************************************************************
@ -48,21 +48,27 @@ static e_blwl_protocol_type string_to_blwl_protocol_type(
}
/********************************************************************
* Parse XML codes of a <programming_clock> to an object of configuration protocol
* Parse XML codes of a <programming_clock> to an object of configuration
*protocol
*******************************************************************/
static void read_xml_ccff_prog_clock(pugi::xml_node& xml_progclk,
const pugiutil::loc_data& loc_data,
ConfigProtocol& config_protocol) {
/* Find the type of configuration protocol */
std::string port_attr =
get_attribute(xml_progclk, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR, loc_data).as_string();
get_attribute(xml_progclk, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR,
loc_data)
.as_string();
std::string indices_attr =
get_attribute(xml_progclk, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR, loc_data).as_string();
get_attribute(xml_progclk, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR,
loc_data)
.as_string();
openfpga::BasicPort port = openfpga::PortParser(port_attr).port();
openfpga::BasicPort port = openfpga::PortParser(port_attr).port();
config_protocol.set_prog_clock_port_ccff_head_indices_pair(port, indices_attr);
config_protocol.set_prog_clock_port_ccff_head_indices_pair(port,
indices_attr);
}
/********************************************************************
@ -162,10 +168,10 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz,
/* Parse the number of configurable regions
* At least 1 region should be defined, otherwise error out
*/
config_protocol.set_num_regions(get_attribute(xml_config_orgz, XML_CONFIG_PROTOCOL_NUM_REGIONS_ATTR,
loc_data,
pugiutil::ReqOpt::OPTIONAL)
.as_int(1));
config_protocol.set_num_regions(
get_attribute(xml_config_orgz, XML_CONFIG_PROTOCOL_NUM_REGIONS_ATTR,
loc_data, pugiutil::ReqOpt::OPTIONAL)
.as_int(1));
if (1 > config_protocol.num_regions()) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_config_orgz),
"Invalid 'num_region=%d' definition. At least 1 region "
@ -177,7 +183,8 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz,
if (config_protocol.type() == CONFIG_MEM_SCAN_CHAIN) {
for (pugi::xml_node xml_progclk : xml_config_orgz.children()) {
/* Error out if the XML child has an invalid name! */
if (xml_progclk.name() != std::string(XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME)) {
if (xml_progclk.name() !=
std::string(XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME)) {
bad_tag(xml_progclk, loc_data, xml_config_orgz, {"programming_clock"});
}
read_xml_ccff_prog_clock(xml_progclk, loc_data, config_protocol);

16
libs/libarchopenfpga/src/write_xml_config_protocol.cpp
View File

@ -32,20 +32,18 @@ static void write_xml_config_organization(std::fstream& fp, const char* fname,
write_xml_attribute(
fp, "circuit_model_name",
circuit_lib.model_name(config_protocol.memory_model()).c_str());
write_xml_attribute(
fp, XML_CONFIG_PROTOCOL_NUM_REGIONS_ATTR,
config_protocol.num_regions());
write_xml_attribute(fp, XML_CONFIG_PROTOCOL_NUM_REGIONS_ATTR,
config_protocol.num_regions());
fp << "/>"
<< "\n";
/* CCFF protocol details */
if (config_protocol.type() == CONFIG_MEM_SCAN_CHAIN) {
if (config_protocol.type() == CONFIG_MEM_SCAN_CHAIN) {
for (openfpga::BasicPort port : config_protocol.prog_clock_ports()) {
fp << "\t\t\t"
<< "<" << XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME;
write_xml_attribute(
fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR,
port.to_verilog_string().c_str());
write_xml_attribute(fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR,
port.to_verilog_string().c_str());
write_xml_attribute(
fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR,
config_protocol.prog_clock_port_ccff_head_indices_str(port).c_str());
@ -55,7 +53,7 @@ static void write_xml_config_organization(std::fstream& fp, const char* fname,
}
/* BL/WL protocol details */
if (config_protocol.type() == CONFIG_MEM_QL_MEMORY_BANK) {
if (config_protocol.type() == CONFIG_MEM_QL_MEMORY_BANK) {
fp << "\t\t\t"
<< "<bl";
write_xml_attribute(
@ -67,7 +65,7 @@ static void write_xml_config_organization(std::fstream& fp, const char* fname,
write_xml_attribute(fp, "num_banks", config_protocol.bl_num_banks());
fp << "/>"
<< "\n";
fp << "\t\t\t"
<< "<wl";
write_xml_attribute(

3
libs/libopenfpgautil/src/openfpga_port.cpp
View File

@ -107,7 +107,8 @@ bool BasicPort::contained(const BasicPort& portA) const {
size_t BasicPort::get_origin_port_width() const { return origin_port_width_; }
std::string BasicPort::to_verilog_string() const {
return get_name() + "[" + std::to_string(get_lsb()) + ":" + std::to_string(get_msb()) + "]";
return get_name() + "[" + std::to_string(get_lsb()) + ":" +
std::to_string(get_msb()) + "]";
}
/************************************************************************

3
libs/libopenfpgautil/src/openfpga_port.h
View File

@ -35,7 +35,8 @@ class BasicPort {
bool contained(const BasicPort& portA)
const; /* Check if a port is contained by this port */
size_t get_origin_port_width() const;
std::string to_verilog_string() const; /* Generate verilog-style string, e.g., a[0:1] */
std::string to_verilog_string()
const; /* Generate verilog-style string, e.g., a[0:1] */
public: /* Mutators */
void set(const BasicPort& basic_port); /* copy */

7
openfpga/src/base/openfpga_read_arch_template.h
View File

@ -4,8 +4,8 @@
* This file includes functions to read an OpenFPGA architecture file
* which are built on the libarchopenfpga library
*******************************************************************/
#include "check_config_protocol.h"
#include "check_circuit_library.h"
#include "check_config_protocol.h"
#include "check_tile_annotation.h"
#include "circuit_library_utils.h"
#include "clock_network_utils.h"
@ -56,9 +56,8 @@ int read_openfpga_arch_template(T& openfpga_context, const Command& cmd,
return CMD_EXEC_FATAL_ERROR;
}
if (false == check_config_protocol(
openfpga_context.arch().config_protocol,
openfpga_context.arch().circuit_lib)) {
if (false == check_config_protocol(openfpga_context.arch().config_protocol,
openfpga_context.arch().circuit_lib)) {
return CMD_EXEC_FATAL_ERROR;
}

47
openfpga/src/utils/check_config_protocol.cpp
View File

@ -5,8 +5,9 @@
* They are made to ease the development in some specific purposes
* Please classify such functions in this file
***********************************************************************/
#include "circuit_library_utils.h"
#include "check_config_protocol.h"
#include "circuit_library_utils.h"
#include "vtr_assert.h"
#include "vtr_log.h"
@ -14,7 +15,8 @@
namespace openfpga {
/********************************************************************
* Check if the programming clock port defined in configuration protocol is a valid global programming clock of a ccff model
* Check if the programming clock port defined in configuration protocol is a
*valid global programming clock of a ccff model
*******************************************************************/
static int check_config_protocol_programming_clock(
const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib) {
@ -24,35 +26,48 @@ static int check_config_protocol_programming_clock(
return num_err;
}
/* Must find a CCFF model */
std::vector<CircuitModelId> ccff_models = circuit_lib.models_by_type(CIRCUIT_MODEL_CCFF);
std::vector<CircuitModelId> ccff_models =
circuit_lib.models_by_type(CIRCUIT_MODEL_CCFF);
if (ccff_models.empty()) {
VTR_LOG_ERROR("Expect at least one CCFF model to be defined in circuit library!\n");
VTR_LOG_ERROR(
"Expect at least one CCFF model to be defined in circuit library!\n");
num_err++;
}
/* Try to match the programming clock port name with the CCFF port name */
for (BasicPort prog_clk_port : config_protocol.prog_clock_ports()) {
bool port_match = false;
for (CircuitModelId ccff_model : ccff_models) {
CircuitPortId circuit_port = circuit_lib.model_port(ccff_model, prog_clk_port.get_name());
for (CircuitModelId ccff_model : ccff_models) {
CircuitPortId circuit_port =
circuit_lib.model_port(ccff_model, prog_clk_port.get_name());
if (circuit_port) {
port_match = true;
/* Ensure this is a programming clock and a global port */
if (!circuit_lib.port_is_global(circuit_port)) {
VTR_LOG_ERROR("Expect the programming clock '%s' to be a global port but not!\n", prog_clk_port.get_name().c_str());
VTR_LOG_ERROR(
"Expect the programming clock '%s' to be a global port but not!\n",
prog_clk_port.get_name().c_str());
num_err++;
}
if (circuit_lib.port_type(circuit_port) != CIRCUIT_MODEL_PORT_CLOCK) {
VTR_LOG_ERROR("Expect the programming clock '%s' to be a clock port but not!\n", prog_clk_port.get_name().c_str());
VTR_LOG_ERROR(
"Expect the programming clock '%s' to be a clock port but not!\n",
prog_clk_port.get_name().c_str());
num_err++;
}
if (!circuit_lib.port_is_prog(circuit_port)) {
VTR_LOG_ERROR("Expect the programming clock '%s' to be a programming port but not!\n", prog_clk_port.get_name().c_str());
VTR_LOG_ERROR(
"Expect the programming clock '%s' to be a programming port but "
"not!\n",
prog_clk_port.get_name().c_str());
num_err++;
}
}
}
if (!port_match) {
VTR_LOG_ERROR("Fail to find a port of any CCFF model that matches the programming clock definition (Expect port name: '%s')!\n", prog_clk_port.get_name().c_str());
VTR_LOG_ERROR(
"Fail to find a port of any CCFF model that matches the programming "
"clock definition (Expect port name: '%s')!\n",
prog_clk_port.get_name().c_str());
num_err++;
}
}
@ -64,22 +79,20 @@ static int check_config_protocol_programming_clock(
* Check if the configuration protocol is valid without any conflict with
* circuit library content.
*******************************************************************/
bool check_config_protocol(
const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib) {
bool check_config_protocol(const ConfigProtocol& config_protocol,
const CircuitLibrary& circuit_lib) {
int num_err = 0;
if (!config_protocol.validate()) {
num_err++;
}
if (!check_configurable_memory_circuit_model(
config_protocol,
circuit_lib)) {
if (!check_configurable_memory_circuit_model(config_protocol, circuit_lib)) {
num_err++;
}
num_err += check_config_protocol_programming_clock(
config_protocol, circuit_lib);
num_err +=
check_config_protocol_programming_clock(config_protocol, circuit_lib);
VTR_LOG("Found %ld errors when checking configuration protocol!\n", num_err);
return (0 == num_err);

6
openfpga/src/utils/check_config_protocol.h
View File

@ -4,8 +4,8 @@
/********************************************************************
* Include header files that are required by function declaration
*******************************************************************/
#include "config_protocol.h"
#include "circuit_library.h"
#include "config_protocol.h"
/********************************************************************
* Function declaration
@ -14,8 +14,8 @@
/* begin namespace openfpga */
namespace openfpga {
bool check_config_protocol(
const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib);
bool check_config_protocol(const ConfigProtocol& config_protocol,
const CircuitLibrary& circuit_lib);
} /* end namespace openfpga */