5d79a3f69f
critical bug fixed when annotating the routing results.
...
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
b91c30191a
add input and output net echo in arch bitstream database
2020-06-17 00:04:55 -06:00
a5055e9d26
add support about loading external fabric key
2020-06-12 13:03:11 -06:00
9dbf536306
add shuffled configurable children support for top module
2020-06-12 11:16:53 -06:00
3499b4d3e7
add fabric key writer for top-level module
2020-06-12 10:41:34 -06:00
278acee216
bug fix for 'build_fabric' command
2020-06-11 23:59:24 -06:00
9167b288b6
add options for fabric key
2020-06-11 21:50:46 -06:00
58807bfcb3
remove simulation settings from openfpga arch data structure
2020-06-11 19:31:16 -06:00
96b58dfdbb
use new simulation setting command in openfpga shell
2020-06-11 19:31:15 -06:00
4a2f6dfae2
add read/write simulation setting commands to openfpga shell
2020-06-11 19:31:15 -06:00
0bee70bee6
finish memory bank configuration protocol support.
2020-06-11 19:31:13 -06:00
0e16ee1030
add configuration bus nets for memory bank decoders at top module
2020-06-11 19:31:13 -06:00
fa8dfc1fbd
add configuration protocol ports to top module for memory bank organization
2020-06-11 19:31:13 -06:00
fbe05963e0
add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
2020-06-11 19:31:12 -06:00
d2d443a988
start developing memory bank and standalone configuration protocol
2020-06-11 19:31:12 -06:00
8b3e79766c
add fast configuration option to fpga_verilog to speed up full testbench simulation
2020-06-11 19:31:12 -06:00
65df309419
bug fixing for frame-based configuration protocol and rename some naming function to be generic
2020-06-11 19:31:10 -06:00
4a0e1cd908
add fabric bitstream data structure and deploy it to Verilog testbench generation
2020-06-11 19:31:10 -06:00
5c5a044c68
add architecture decoder (for frame-based config memory) to Verilog writer
2020-06-11 19:31:09 -06:00
290dd1a8a6
add frame decoder builder to all the module graph builder except the top-level
2020-06-11 19:31:09 -06:00
8864920460
add frame-based memory module builder
2020-06-11 19:31:09 -06:00
3a26bb5eef
add advanced check in configurable memories
2020-06-11 19:31:09 -06:00
bba476fef4
add explicit port mapping support to Verilog testbench generator
2020-06-11 19:31:07 -06:00
e089b0ef22
use constant string for inverted port naming
2020-06-11 19:31:07 -06:00
8915d10d27
add verbose output option to configure port disable timing writer
2020-06-11 19:31:07 -06:00
f52b5d5b4c
use error code in read_arch command
2020-06-11 19:31:07 -06:00
e9ceedb01b
use constant openfpga context in SDC generator
2020-06-11 19:31:07 -06:00
13f591cacf
add new command to disable timing for configure ports of programmable modules
2020-06-11 19:31:06 -06:00
4c0953415b
add configuration chain sdc writer
2020-06-11 19:31:06 -06:00
8d2360a710
simplify include_netlist.v
2020-06-11 19:31:05 -06:00
5a8c05378e
add --depth option to fabric hierarchy writer
2020-06-11 19:31:04 -06:00
d9dc7160a7
minor fix on the hierarchy writer in SDC generator
2020-06-11 19:31:04 -06:00
c651df6421
add hierarchy writer to SDC generator
2020-06-11 19:31:04 -06:00
6aff33dd35
add fabric hierarchy writer
2020-06-11 19:31:04 -06:00
8726c618eb
add time unit support on SDC generator. Now users can define time_unit thru cmd-line options
2020-06-11 19:31:03 -06:00
7e82c23f52
now add SDC generator supports both hierarchical and flatten in writing timing constraints
2020-06-11 19:31:03 -06:00
d0793d9029
now disable_sb_output support wildcard
2020-06-11 19:31:02 -06:00
8695c5ee78
add options to use general-purpose wildcards in SDC generator
2020-06-11 19:31:02 -06:00
e811f8bb21
plug in netlist manager and now the include_netlist appears in one unique file
2020-04-23 20:42:11 -06:00
87b17fc25f
add netlist manager data structure
2020-04-23 18:59:09 -06:00
68b7991a46
bug fixed for sdc on memory blocks
2020-04-21 13:37:56 -06:00
d325bede68
add fabric bitstream writer
2020-04-21 12:02:10 -06:00
e10cafe0a5
Critical patch on repacking about wire LUT support.
...
Previously, the wire LUT identification is too naive and does not consider all the cases
2020-04-19 16:42:31 -06:00
b9dab2baaf
add exit codes to command execution in shell context
2020-04-08 16:18:05 -06:00
1fb37f4c71
improve directory creator to support same functionality as 'mkdir -p'
2020-04-08 12:55:09 -06:00
cbcd1d20d4
fixed memory leakage in pb_pin fixup
2020-04-07 16:24:04 -06:00
5a04da2082
fix memory leakage in openfpga title
2020-04-07 16:14:41 -06:00
bcb86801fa
bug fixed in gpio naming for module manager ports
2020-04-05 17:26:44 -06:00
e601a648cc
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
2020-03-27 19:07:34 -06:00
7c9c2451f2
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
2020-03-27 16:03:42 -06:00
329b0a9cf1
add options to enable SDC constraints on zero-delay paths
2020-03-25 15:55:30 -06:00
c2e5d6b8e2
add options to dsiable SDC for non-clock global ports
2020-03-25 14:38:13 -06:00
787dc8ce83
added ASCII OpenFPGA logo in shell interface
2020-03-25 11:16:04 -06:00
9e4e12aae9
fixed echo message in the compression rate of gsb uniquifying
2020-03-22 16:13:04 -06:00
ff474d87de
fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs
2020-03-22 16:11:00 -06:00
3958ac2494
fix bugs in flow manager on default compress routing problems
2020-03-22 15:26:15 -06:00
7b9384f3b2
add write_gsb command to shell interface
2020-03-21 19:40:26 -06:00
9a518e8bb6
bug fixed for tileable rr_graph builder for more 4x4 fabrics
2020-03-21 18:07:00 -06:00
c0e8d98c6f
bug fixed in tile direct builder
2020-03-21 12:43:56 -06:00
aff73bdd74
deployed edge sorting and make it as an option to link_arch command
2020-03-08 15:59:53 -06:00
37423729ec
bug fixing for naming the duplicated pins
2020-03-07 15:44:57 -07:00
7fcd27e000
now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
2020-03-03 12:29:58 -07:00
3241d8bd37
put analysis sdc writer online. Minor bug in redudant '/' to be fixed
2020-03-02 19:54:18 -07:00
037c7e5c43
adapt top-level function for analysis SDC writer
2020-03-02 17:58:44 -07:00
a17c14c363
clean-up command addition and add fabric bitstream building to sample script
2020-03-02 10:39:19 -07:00
aa66042dfb
move simulation setting annotation to a separated source file
2020-02-29 15:19:02 -07:00
7b18f7cd09
now the auto select number of clocks in simulation is online
2020-02-29 13:29:16 -07:00
542fadaaae
allow users to use VPR critical path delay in OpenFPGA simulation
2020-02-28 12:10:27 -07:00
de8425874c
use user defined critical path delay in SDC generation
2020-02-28 11:24:39 -07:00
092e10afda
bring pnr sdc generator online and fixed minor bugs in bitstream writing
2020-02-28 11:14:50 -07:00
9b769cd8e4
bug fix for using renamed i/o names
2020-02-27 16:37:20 -07:00
078f72320f
debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
2020-02-27 13:24:26 -07:00
f558405887
ported verilog testbench generator online. Split from fabric generator. Testing to be done
2020-02-27 12:33:09 -07:00
b3796b0818
build io location map
2020-02-26 19:58:18 -07:00
25e0583636
add io location map data structure and start porting verilog testbench generator
2020-02-26 17:10:57 -07:00
a26d31b87f
make write bitstream online
2020-02-26 11:09:23 -07:00
4024ed63cb
add truth table build up for physical LUTs
2020-02-25 22:39:42 -07:00
8e9660b816
add mapped block fast look-up as placement annotation
2020-02-24 16:09:29 -07:00
2d17395e13
start integrating fpga_bitstream. Bring data structures online
2020-02-22 23:04:42 -07:00
4abaef14b5
bug fixed in pb_pin fix-up. This is due to A CRITICAL BUG IN PHYSICAL_TILE PIN MAPPING!!!
2020-02-20 20:50:59 -07:00
3e07d7d5e0
finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
2020-02-20 20:26:20 -07:00
fdb27c5a6b
move lb_rr_graph construction to repack command
2020-02-20 13:24:34 -07:00
409b3f6896
add lb_rr_graph builder for the refactored version
2020-02-17 21:11:56 -07:00
8e97443410
start working on repack
2020-02-17 17:57:43 -07:00
62e4f14e30
add lb_rr_graph to device annotation
2020-02-17 17:26:27 -07:00
6c69b52ded
Add missing file
2020-02-17 17:11:29 -07:00
e37ac8a098
add grid module Verilog writer
2020-02-16 16:04:41 -07:00
c6c3ef71f3
adapt all the Verilog submodule writers and bring it onlien
2020-02-16 13:35:18 -07:00
bf54be3d00
add option data structure for FPGA Verilog
2020-02-15 21:39:47 -07:00
da79ef687c
add missing files
2020-02-15 20:54:37 -07:00
8b0df8632c
bring fpga verilog create directory online
2020-02-15 20:38:45 -07:00
539f13720a
tile direct supports inter-column/inter-row direct connections
2020-02-15 13:42:53 -07:00
213c611c0b
add tile direct builder
2020-02-14 22:21:32 -07:00
afe8278670
put routing module builder online
2020-02-13 17:35:29 -07:00
89086ed080
add verbose output to build grid module
2020-02-13 15:38:26 -07:00
072965cd64
make grid module builder online; basic support on physical tiles
2020-02-13 15:27:16 -07:00
895d5b5a0a
add utils for grid module builder
2020-02-12 20:25:05 -07:00
fddd3c9463
add mux module builder
2020-02-12 19:45:14 -07:00
f11832b8cf
start integrating module graph builder
2020-02-12 17:53:23 -07:00
13fadd0f91
move compact routing hierarchy to build_fabric command
2020-02-12 15:49:47 -07:00
tangxifan