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add mux module builder

This commit is contained in:
tangxifan 2020-02-12 19:45:14 -07:00
parent ea7d879b4f
commit fddd3c9463
7 changed files with 1590 additions and 3 deletions
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28
openfpga/src/base/openfpga_reserved_words.h Normal file
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@ -0,0 +1,28 @@
/********************************************************************
* This file includes all the reserved words that are used in
* naming module, blocks, instances and cells in FPGA X2P support,
* including:
* Verilog generation, SPICE generation and bitstream generation
*******************************************************************/
#ifndef OPENFPGA_RESERVED_WORDS_H
#define OPENFPGA_RESERVED_WORDS_H
/* Grid naming constant strings */
constexpr char* GRID_MODULE_NAME_PREFIX = "grid_";
/* Memory naming constant strings */
constexpr char* GRID_MEM_INSTANCE_PREFIX = "mem_";
constexpr char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_";
constexpr char* CONNECTION_BLOCK_MEM_INSTANCE_PREFIX = "mem_";
constexpr char* MEMORY_MODULE_POSTFIX = "_mem";
/* Multiplexer naming constant strings */
constexpr char* MUX_BASIS_MODULE_POSTFIX = "_basis";
constexpr char* GRID_MUX_INSTANCE_PREFIX = "mux_";
constexpr char* SWITCH_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
constexpr char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
/* Bitstream file strings */
constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml";
#endif

4
openfpga/src/fabric/build_device_module.cpp
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@ -10,7 +10,7 @@
#include "build_essential_modules.h"
#include "build_decoder_modules.h"
//#include "build_mux_modules.h"
#include "build_mux_modules.h"
//#include "build_lut_modules.h"
//#include "build_wire_modules.h"
//#include "build_memory_modules.h"
@ -53,7 +53,7 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
openfpga_ctx.arch().circuit_lib);
/* Build multiplexer modules */
//build_mux_modules(module_manager, mux_lib, arch.spice->circuit_lib);
build_mux_modules(module_manager, openfpga_ctx.mux_lib(), openfpga_ctx.arch().circuit_lib);
/* Build LUT modules */
//build_lut_modules(module_manager, arch.spice->circuit_lib);

89
openfpga/src/fabric/build_module_graph_utils.cpp Normal file
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/********************************************************************
* This file includes most utilized functions that are used to
* build module graphs
********************************************************************/
#include <vector>
/* Headers from vtrutil library */
#include "vtr_assert.h"
#include "openfpga_naming.h"
#include "build_module_graph_utils.h"
/* begin namespace openfpga */
namespace openfpga {
/********************************************************************
* Find input port of a buffer/inverter module
********************************************************************/
ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manager,
const ModuleId& module_id,
const CircuitLibrary& circuit_lib,
const CircuitModelId& model_id,
const e_circuit_model_port_type& port_type) {
/* We must have a valid module id */
VTR_ASSERT(true == module_manager.valid_module_id(module_id));
/* Check the type of model */
VTR_ASSERT(CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(model_id));
/* Add module nets to wire to the buffer module */
/* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */
std::vector<CircuitPortId> model_ports = circuit_lib.model_ports_by_type(model_id, port_type, true);
VTR_ASSERT(1 == model_ports.size());
/* Find the input and output module ports */
ModulePortId module_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(model_ports[0]));
VTR_ASSERT(true == module_manager.valid_module_port_id(module_id, module_port_id));
return module_port_id;
}
/********************************************************************
* Add inverter/buffer module to a parent module
* and complete the wiring to the input port of inverter/buffer
* This function will return the wire created for the output port of inverter/buffer
*
* parent_module
* +-----------------------------------------------------------------
* |
* | input_net output_net
* | | |
* | v +---------------+ v
* | src_module_port --------->| child_module |-------->
* | +---------------+
*
********************************************************************/
ModuleNetId add_inverter_buffer_child_module_and_nets(ModuleManager& module_manager,
const ModuleId& parent_module,
const CircuitLibrary& circuit_lib,
const CircuitModelId& model_id,
const ModuleNetId& input_net) {
/* We must have a valid module id */
VTR_ASSERT(true == module_manager.valid_module_id(parent_module));
std::string module_name = circuit_lib.model_name(model_id);
ModuleId child_module = module_manager.find_module(module_name);
VTR_ASSERT(true == module_manager.valid_module_id(child_module));
ModulePortId module_input_port_id = find_inverter_buffer_module_port(module_manager, child_module, circuit_lib, model_id, CIRCUIT_MODEL_PORT_INPUT);
ModulePortId module_output_port_id = find_inverter_buffer_module_port(module_manager, child_module, circuit_lib, model_id, CIRCUIT_MODEL_PORT_OUTPUT);
/* Port size should be 1 ! */
VTR_ASSERT(1 == module_manager.module_port(child_module, module_input_port_id).get_width());
VTR_ASSERT(1 == module_manager.module_port(child_module, module_output_port_id).get_width());
/* Instanciate a child module */
size_t child_instance = module_manager.num_instance(parent_module, child_module);
module_manager.add_child_module(parent_module, child_module);
/* Use the net to connect to the input net of buffer */
module_manager.add_module_net_sink(parent_module, input_net, child_module, child_instance, module_input_port_id, 0);
/* Create a net to bridge the input inverter and LUT MUX */
ModuleNetId output_net = module_manager.create_module_net(parent_module);
module_manager.add_module_net_source(parent_module, output_net, child_module, child_instance, module_output_port_id, 0);
return output_net;
}
} /* end namespace openfpga */

38
openfpga/src/fabric/build_module_graph_utils.h Normal file
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@ -0,0 +1,38 @@
#ifndef BUILD_MODULE_GRAPH_UTILS_H
#define BUILD_MODULE_GRAPH_UTILS_H
/********************************************************************
* Include header files that are required by function declaration
*******************************************************************/
#include <string>
#include <vector>
#include "vtr_geometry.h"
#include "circuit_library.h"
#include "openfpga_side_manager.h"
#include "vpr_types.h"
#include "module_manager.h"
/********************************************************************
* Function declaration
*******************************************************************/
/* begin namespace openfpga */
namespace openfpga {
ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manager,
const ModuleId& module_id,
const CircuitLibrary& circuit_lib,
const CircuitModelId& model_id,
const e_circuit_model_port_type& port_type);
ModuleNetId add_inverter_buffer_child_module_and_nets(ModuleManager& module_manager,
const ModuleId& parent_module,
const CircuitLibrary& circuit_lib,
const CircuitModelId& model_id,
const ModuleNetId& input_net);
} /* end namespace openfpga */
#endif

1408
openfpga/src/fabric/build_mux_modules.cpp Normal file
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24
openfpga/src/fabric/build_mux_modules.h Normal file
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#ifndef BUILD_MUX_MODULES_H
#define BUILD_MUX_MODULES_H
/********************************************************************
* Include header files that are required by function declaration
*******************************************************************/
#include "circuit_library.h"
#include "mux_library.h"
#include "module_manager.h"
/********************************************************************
* Function declaration
*******************************************************************/
/* begin namespace openfpga */
namespace openfpga {
void build_mux_modules(ModuleManager& module_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib);
} /* end namespace openfpga */
#endif

2
openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
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@ -149,7 +149,7 @@
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos"/>
<design_technology type="cmos" fracturable_lut="true"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>