add decoder module builder
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tangxifan
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/***************************************************************************************
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* This file includes functions that are used to build modules for decoders, including:
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* 1. Local decoders used by multiplexers ONLY
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* 2. Decoders used by grid/routing/top-level module for memory address decoding
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***************************************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_log.h"
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#include "vtr_assert.h"
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#include "vtr_time.h"
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#include "openfpga_naming.h"
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#include "decoder_library_utils.h"
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#include "module_manager_utils.h"
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#include "build_decoder_modules.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/***************************************************************************************
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* Create a module for a decoder with a given output size
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*
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* Inputs
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* | | ... |
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* v v v
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* +-----------+
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* / \
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* / Decoder \
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* +-----------------+
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* | | | ... | | |
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* v v v v v v
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* Outputs
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*
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* The outputs are assumes to be one-hot codes (at most only one '1' exist)
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* Considering this fact, there are only num_of_outputs conditions to be encoded.
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* Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2))
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***************************************************************************************/
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static
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void build_mux_local_decoder_module(ModuleManager& module_manager,
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const DecoderLibrary& decoder_lib,
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const DecoderId& decoder) {
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/* Get the number of inputs */
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size_t addr_size = decoder_lib.addr_size(decoder);
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size_t data_size = decoder_lib.data_size(decoder);
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/* TODO: create a name for the local encoder */
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std::string module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size);
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId module_id = module_manager.add_module(module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(module_id));
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/* Add module ports */
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/* Add each input port */
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BasicPort addr_port(generate_mux_local_decoder_addr_port_name(), addr_size);
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module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT);
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/* Add each output port */
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BasicPort data_port(generate_mux_local_decoder_data_port_name(), data_size);
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module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT);
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/* Data port is registered. It should be outputted as
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* output reg [lsb:msb] data
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*/
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module_manager.set_port_is_register(module_id, data_port.get_name(), true);
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/* Add data_in port */
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BasicPort data_inv_port(generate_mux_local_decoder_data_inv_port_name(), data_size);
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VTR_ASSERT(true == decoder_lib.use_data_inv_port(decoder));
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module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT);
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}
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/***************************************************************************************
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* This function will generate all the unique Verilog modules of local decoders for
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* the multiplexers used in a FPGA fabric
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* It will reach the goal in two steps:
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* 1. Find the unique local decoders w.r.t. the number of inputs/outputs
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* We will generate the subgraphs from the multiplexing graph of each multiplexers
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* The number of memory bits is the number of outputs.
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* From that we can infer the number of inputs of each local decoders.
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* Here is an illustrative example of how local decoders are interfaced with multi-level MUXes
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*
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* +---------+ +---------+
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* | Local | | Local |
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* | Decoder | | Decoder |
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* | A | | B |
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* +---------+ +---------+
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* | ... | | ... |
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* v v v v
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* +--------------+ +--------------+
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* | MUX Level 0 |--->| MUX Level 1 |
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* +--------------+ +--------------+
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* 2. Generate local decoder Verilog modules using behavioral description.
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* Note that the implementation of local decoders can be dependent on the technology
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* and standard cell libraries.
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* Therefore, behavioral Verilog is used and the local decoders should be synthesized
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* before running the back-end flow for FPGA fabric
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* See more details in the function print_verilog_mux_local_decoder() for more details
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***************************************************************************************/
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void build_mux_local_decoder_modules(ModuleManager& module_manager,
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const MuxLibrary& mux_lib,
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const CircuitLibrary& circuit_lib) {
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vtr::ScopedStartFinishTimer timer("Build local encoder (for multiplexers) modules");
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/* Create a library for local encoders with different sizes */
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DecoderLibrary decoder_lib;
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/* Find unique local decoders for unique branches shared by the multiplexers */
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for (auto mux : mux_lib.muxes()) {
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/* Local decoders are need only when users specify them */
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CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux);
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/* If this MUX does not need local decoder, we skip it */
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if (false == circuit_lib.mux_use_local_encoder(mux_circuit_model)) {
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continue;
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}
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const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
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/* Create a mux graph for the branch circuit */
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std::vector<MuxGraph> branch_mux_graphs = mux_graph.build_mux_branch_graphs();
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/* Add the decoder to the decoder library */
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for (auto branch_mux_graph : branch_mux_graphs) {
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/* The decoder size depends on the number of memories of a branch MUX.
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* Note that only when there are >=2 memories, a decoder is needed
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*/
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size_t decoder_data_size = branch_mux_graph.num_memory_bits();
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if (0 == decoder_data_size) {
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continue;
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}
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/* Try to find if the decoder already exists in the library,
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* If there is no such decoder, add it to the library
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*/
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add_mux_local_decoder_to_library(decoder_lib, decoder_data_size);
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}
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}
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/* Generate Verilog modules for the found unique local encoders */
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for (const auto& decoder : decoder_lib.decoders()) {
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build_mux_local_decoder_module(module_manager, decoder_lib, decoder);
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}
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}
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} /* end namespace openfpga */
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#ifndef BUILD_DECODER_MODULES_H
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#define BUILD_DECODER_MODULES_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include "module_manager.h"
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#include "mux_library.h"
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#include "circuit_library.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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void build_mux_local_decoder_modules(ModuleManager& module_manager,
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const MuxLibrary& mux_lib,
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const CircuitLibrary& circuit_lib);
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} /* end namespace openfpga */
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#endif
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@ -9,7 +9,7 @@
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#include "vtr_time.h"
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#include "build_essential_modules.h"
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//#include "build_decoder_modules.h"
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#include "build_decoder_modules.h"
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//#include "build_mux_modules.h"
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//#include "build_lut_modules.h"
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//#include "build_wire_modules.h"
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@ -49,7 +49,8 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
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build_essential_modules(module_manager, openfpga_ctx.arch().circuit_lib);
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/* Build local encoders for multiplexers, this MUST be called before multiplexer building */
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//build_mux_local_decoder_modules(module_manager, mux_lib, arch.spice->circuit_lib);
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build_mux_local_decoder_modules(module_manager, openfpga_ctx.mux_lib(),
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openfpga_ctx.arch().circuit_lib);
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/* Build multiplexer modules */
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//build_mux_modules(module_manager, mux_lib, arch.spice->circuit_lib);
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@ -150,7 +150,7 @@ void build_gate_module(ModuleManager& module_manager,
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***********************************************/
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void build_essential_modules(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib) {
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vtr::ScopedStartFinishTimer timer("Build essential (inverter/buffer/logic gate) modules...");
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vtr::ScopedStartFinishTimer timer("Build essential (inverter/buffer/logic gate) modules");
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for (const auto& circuit_model : circuit_lib.models()) {
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/* Add essential modules upon on demand: only when it is not yet in the module library */
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