bf2b1da801
[doc] add the new command file format to documentation
2022-07-26 14:06:07 -07:00
21a0415ff3
Update compile.rst
2022-07-21 17:52:21 -07:00
929c74b3b0
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into hotfix_reg
2022-05-23 09:11:18 +08:00
7a0f796b7c
[doc] add missing file link and show version number in frontpage README
2022-05-22 15:27:22 +08:00
78313b3593
[Misc] Now version number is in a separated file; Cmakefile and doc read the file and build version number on fly; CI can also update version
2022-05-22 15:22:43 +08:00
1794578b49
[doc] code format
2022-05-22 14:04:12 +08:00
07df4611e8
[doc] more tips
2022-05-22 13:46:13 +08:00
61a1462c21
[doc] add guidelines about running regression tests
2022-05-22 13:44:48 +08:00
daae02a614
Minor documentation update
2022-05-08 13:03:16 -06:00
1e243650b9
Added option to copy example projects
2022-05-03 14:06:16 -06:00
42567d8178
Updated docuementation
2022-05-02 12:56:31 -06:00
907308ee0f
[Doc] Update bitstream distribution file format
2022-03-29 20:09:24 +08:00
781250f0bb
Fix a small typo to trigger the CI flow.
2022-03-22 16:36:45 -07:00
6ff69d26b9
[Doc] An example to the documentation about the new feature in tile_annotation
2022-03-20 13:12:13 +08:00
123bb70cb3
[Doc] More explanantion on the use of config_enable attribute for circuit ports
2022-02-23 15:53:58 -08:00
b78e58d9bf
[Doc] Update doc about big endian syntax in bus group file format
2022-02-18 23:07:18 -08:00
8116141210
[Doc] Update documentation on the bus group feature
2022-02-18 15:46:25 -08:00
37d8617a5c
[Doc] Update due to new options
2022-02-17 19:45:37 -08:00
4a78bcf5d3
[Doc] update file format about bus group
2022-02-17 15:15:05 -08:00
f5e0d685cf
[Doc] Adjust figure width
2022-02-17 14:29:09 -08:00
796428d848
[Doc] Add documentation about bus group file format
2022-02-17 14:22:21 -08:00
2b5fded2a9
[Doc] Update documentation on the new option
2022-02-01 13:25:58 -08:00
b7b0a2a5d8
[Doc] Update doc about the new option
2022-02-01 12:19:26 -08:00
63f44adf15
[FPGA-Verilog] Now have a new option ``--use_relative_path``
2022-01-31 12:48:05 -08:00
a9a56686e2
[Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml``
2022-01-26 11:10:29 -08:00
25143d07f1
[FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files
2022-01-25 13:37:54 -08:00
a4659020f2
Merge branch 'master' into time_stamp
2022-01-25 12:11:35 -08:00
62b57b05d2
[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
2022-01-25 12:09:08 -08:00
758453f725
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
2022-01-21 02:21:00 +05:00
bd158311c5
Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
2022-01-18 14:07:41 +05:00
588ee14920
Merge branch 'master' into issue-483
2022-01-18 13:38:12 +05:00
fb2e4377c8
Added missing changes from previous commit.
2022-01-17 19:42:40 +05:00
2b008177e7
Updated documentation.
2022-01-17 14:58:20 +05:00
54d4f30592
OpenFPGA Documentation updated for yosys only support
2022-01-14 16:14:48 +05:00
80c6d5887d
Merge branch 'ql_mem_bank_opensource' of https://github.com/RapidSilicon/OpenFPGA_RS into ql_mem_bank
2021-12-29 10:57:46 -08:00
b2ba0d0c42
[Doc] Add version naming convention to developer guidelines
2021-12-22 15:12:14 -08:00
236910cde4
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-12-09 00:00:21 +05:00
1e5afb985c
Update contact.rst
2021-11-30 20:25:15 -08:00
1ea56b2d18
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-11-18 00:00:55 +05:00
a355977420
Adding Yosys+Verific support.
2021-10-29 18:34:27 +05:00
b8d5920529
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
2021-10-28 15:45:58 -07:00
130805d50c
Updated CI documentation
2021-10-21 15:17:30 -06:00
e0cfd46ec7
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-10-14 19:25:31 +05:00
57159fc121
[Doc] Update documentation for the new syntax in configuration protocol and fabric key file format
2021-10-10 17:46:45 -07:00
40b589dc6d
[Doc] Update documentation about the clock definition for programming clocks in simulation settings
2021-10-06 13:50:33 -07:00
03bcf6dee5
[Doc] Update documenation for the new option ``--keep_dont_care_bits``
2021-10-05 19:23:42 -07:00
ff339312f6
[Doc] Update documentation about the limitations of multi-region configuration protocols
2021-10-05 11:55:10 -07:00
9a7e0f761a
[Doc] Add fabric bitstream file format for QL memory bank
2021-10-04 12:29:49 -07:00
a01fa7c282
[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
2021-10-04 12:09:42 -07:00
b0a97a7052
[Doc] Update doc about WLR usage for QL memory bank
2021-09-27 10:24:04 -07:00
f9bceff33a
[Doc] Update documentation for the flatten BL/WL protocols
2021-09-25 20:44:45 -07:00
10774dc15c
[Doc] Updated documentation about new syntax in fabric key
2021-09-21 17:01:52 -07:00
d9d959709c
[Doc] Add missing figures
2021-09-20 20:31:53 -07:00
3146d2484f
[Doc] Update documentation on the WLR definition for circuit model
2021-09-20 17:21:33 -07:00
73d21c9730
[Doc] Update doc about how to use the QuickLogic memory bank
2021-09-10 15:30:37 -07:00
801b91f776
Merge branch 'master' into tutorials
2021-08-31 17:17:40 -07:00
1c09b8c3e0
fixed python instruction
2021-08-17 10:18:51 -06:00
814d290463
Merge branch 'master' into tutorials
2021-08-05 10:24:34 -06:00
c867c7e628
Update index to include FAQ page
2021-07-28 10:14:31 -06:00
2bb76e4a82
Update to include suggested changes
2021-07-28 10:13:25 -06:00
17d3fb5d5e
Add FAQ to source folder to go along in appendix
2021-07-28 10:10:17 -06:00
a8a8c25a21
Update compile.rst
2021-07-26 15:18:23 -06:00
1c0bec1c5a
Update compile.rst
2021-07-26 15:17:25 -06:00
3ce866f2eb
Update compile.rst
2021-07-26 15:12:59 -06:00
43afaca17c
[Doc] Add more details about the new syntax
2021-07-01 23:51:54 -06:00
0851075bc9
[Doc] Update documentation about the new feature in pin constraint file
2021-07-01 23:47:36 -06:00
ac9046b7d2
[Doc] Remove ``define_simulation.v`` since it is no longer needed.
2021-06-29 15:38:35 -06:00
30027b8c15
[Doc] Update doc to deprecate anything related to '--support_icarus_simulator' and '--include_signal_init'
2021-06-25 15:27:15 -06:00
11d0283771
[Doc] Remove option '--support_icarus_simulator'. Add option '--embed_bitstream'
2021-06-25 15:11:12 -06:00
507f5ee54c
[Doc] Update documentation about time unit support in writing simulation file
2021-06-25 10:34:43 -06:00
8e2ba718d0
[Doc] update documentation on the new option '--testbench_type'
2021-06-25 10:16:48 -06:00
779437cd37
[Doc] Update documentation to remove out-of-date options related to signal_init
2021-06-24 17:07:15 -06:00
de550ac550
Merge branch 'master' into tutorials
2021-06-16 14:00:31 -06:00
7787fe9795
update reference to match doc page
2021-06-16 12:46:43 -06:00
858bb2f21e
fix mistake in first line of page
2021-06-16 12:45:04 -06:00
624e9f3bb7
Update notation at top to match pages in doc
2021-06-16 12:44:01 -06:00
ece6e92f06
Add video at top of page
2021-06-16 12:29:17 -06:00
7a303463c3
Update shell_shortcuts.rst
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Update grammar. <_openfpga_task_args> no longer works
2021-06-14 15:34:13 -06:00
5e8b5d641f
Update compile.rst
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update grammar
2021-06-14 14:51:19 -06:00
1a2ced678e
Update tech_highlights.rst
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Update grammar and add link to standard_cell_library tutorial
2021-06-14 14:34:12 -06:00
d0549f10b3
Make a :ref: for tutorial
2021-06-14 14:28:21 -06:00
9585e1d3b5
[Doc] Update documentation about 'default_net_type' option in testbench generators
2021-06-14 14:00:34 -06:00
dc13325639
Update motivation.rst
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Fixing grammar and spacing
2021-06-14 13:44:20 -06:00
b719419931
[Doc] Update documentation on the FPGA-Verilog commands in openfpga shell; Deprecated the 'write_verilog_testbench' command
2021-06-09 16:59:02 -06:00
54a53bc988
[Doc] Update documentation on the minor changes on bitstream file for memory bank protocol
2021-06-07 17:58:00 -06:00
0fee741008
[Doc] Update documentation on the minor changes on fabric bitstream file format
2021-06-07 14:22:35 -06:00
c30be6e95e
[Doc] Update documentation about the fast configuration for write bitstream command
2021-06-04 20:00:28 -06:00
059e74b4ef
[Doc] Add --fast configuration option to documentation for 'write_full_testbench'
2021-06-04 15:17:00 -06:00
b83d8826fb
[Doc] Update documentation on the testbench organization/waveforms
2021-06-03 16:54:13 -06:00
9bcaa820ae
[Doc] Update documentation for the new command 'write_full_testbench'
2021-06-03 16:18:07 -06:00
16ae23f33e
[Doc] Update notes about compilation guidelines
2021-05-24 16:26:59 -06:00
9b40e74e25
[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
2021-05-24 15:24:50 -06:00
21a18069a1
[Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples
2021-05-24 14:50:55 -06:00
b6b98a75b8
[Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model;
2021-05-24 13:03:40 -06:00
24f83f0058
[Doc] Update documentation about the new command 'report_bitstream_distribution'
2021-05-07 11:54:33 -06:00
1bae59dc6a
[Doc] Update documentation for the write_io_mapping command
2021-04-27 14:54:57 -06:00
d7426808ba
Merge pull request #299 from hitblunders/master
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Updated compile.rst
2021-04-26 00:26:07 -06:00
62dc5a3856
[Doc] Update documentation about the new syntax introduced for pin binding between operating modes and physical modes
2021-04-24 16:02:24 -06:00
cc92c27fde
Update compile.rst
2021-04-24 14:01:52 +05:30
2e1cc5499d
[Doc] Add disclaimer for limitations when using repack pin constraints
2021-04-21 14:14:54 -06:00
9b3dcc65bd
[Doc] Add new bitstream setting syntex 'interconnect' to documentation
2021-04-19 16:37:21 -06:00
986ea492f6
Fix grammar line 38: lookup table ->Look-Up Table
2021-04-19 14:16:40 -06:00
bc6e9746c2
Fix more grammar mistakes
2021-04-19 09:48:42 -06:00
8431337f39
Fix grammar errors in fig captions and elsewhere
2021-04-19 09:36:13 -06:00
86c856d35a
Fix reference links
2021-04-19 09:25:54 -06:00
cd6beb5789
Add one more link to fabric_netlists
2021-04-19 09:14:47 -06:00
f8810940c3
Update links
2021-04-19 09:10:17 -06:00
fcb7ee3283
Update to properly reference fabric netlist page
2021-04-19 09:05:30 -06:00
5010fb1e7f
Update hyperlinks
2021-04-19 08:52:05 -06:00
291638ee0f
Trying to resolve hyperlink to right location
2021-04-19 08:45:02 -06:00
beed1ce31e
replace hyperlink with more stable :ref: link
2021-04-19 08:38:09 -06:00
410c6a12ff
Update figures to be more accurate and clean
2021-04-16 11:46:12 -06:00
221822f0f0
update figures to correctly display out ports
2021-04-16 11:33:01 -06:00
423d814730
Update to include new figures
2021-04-13 16:04:20 -06:00
eff784e77b
Upload new figures for spypad tutorial
2021-04-13 15:53:51 -06:00
46f60d0704
Provide more explanation in Pre-Built Spypads
2021-04-12 18:10:36 -06:00
0606479bf8
Edit figures to better fit page
2021-04-12 17:53:31 -06:00
bb5cd1de47
Update to fix :numref: error example figure
2021-04-12 17:09:16 -06:00
a0b01dccc7
Update spypads_tutorial.rst to address comments
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Add links to github OpenFPGA architecture files, reference fig_gpout_ports, instead of emphasize lines switch to numbering the important lines
2021-04-12 17:02:56 -06:00
64e8e623a5
Update to fix links to proper syntax
2021-04-12 16:14:00 -06:00
bad49cdb75
Update to change Spypads to spypads
2021-04-12 16:07:38 -06:00
1744ce594e
Rename Spypads_tutorial.rst to spypads_tutorial.rst
2021-04-12 16:06:44 -06:00
90df365259
Fix a spacing issue on line 250
2021-04-12 14:21:53 -06:00
198882da89
Update link to From Verilog to Verification
2021-04-12 14:20:40 -06:00
b176ca6c0c
Update to improve readability
2021-04-12 14:13:41 -06:00
a2c2b634e6
Update link for _user_defined_template.v
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This ensures it goes to the correct page after pull request 274 no longer works
2021-04-12 14:00:54 -06:00
f626b17d04
Update user_defined_temp_tutorial
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Change "example" in the beginning of the page to "tutorial" for clarity
2021-04-12 13:58:19 -06:00
9b7001bc0f
Merge branch 'master' into tutorials
2021-04-10 17:16:09 -06:00
e5b47b7d3d
[Doc] Update documentation on the changes on fabric bitstream file formats
2021-04-10 15:45:39 -06:00
62da6b467d
Update tutorial to correctly display code
2021-04-09 16:15:44 -06:00
47dd6f8018
Update to include spypads tutorial
2021-04-09 16:04:37 -06:00
ce2e9c177b
Add figures for spypads tutorial
2021-04-09 16:03:41 -06:00
456a553884
Add Spypads tutorial
2021-04-09 16:02:37 -06:00
c6ae2a9b17
Fix opening paragraph
2021-04-09 09:15:25 -06:00
1d97cbf9b2
Update to improve readability
2021-04-09 08:38:20 -06:00
1534a3a7c7
Update Figure Citations
2021-04-02 16:02:41 -06:00
b4945a3c1e
Update to change information errors
2021-04-02 15:56:56 -06:00
d5ec17867d
Add files via upload
2021-04-02 14:49:58 -06:00
0655cda94d
Rescale PNG images downward
2021-04-02 14:45:47 -06:00
dc725dfd6f
Update to use cropped GTKWave PNGs
2021-04-02 14:43:37 -06:00
15fcf03e31
Crop GTKWaveforms
2021-04-02 14:42:23 -06:00
75891f800d
Update to fix reference link and shrink PNGs
2021-04-02 14:24:51 -06:00
71b96b9169
Update tutorial to swap in PNGs and fix errors
2021-04-02 14:22:03 -06:00
269776bb9c
Add Waveforms from GTKWave
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Upload a variety of different formats for the waveforms to find which one looks the best for the Cell Libraries tutorial page
2021-04-02 14:09:23 -06:00
dc991a912e
Update to fix grammar and spelling errors
2021-04-02 10:59:18 -06:00
b6feecc4c3
Update to fix SVG files to show data better
2021-04-02 10:47:36 -06:00
3c27027f76
Add files via upload
2021-04-02 10:46:51 -06:00
cfa2d7042d
Update Custom_Waveforms.svg
2021-04-02 10:44:36 -06:00
4c35df0df3
Update open_cell_libraries_tutorial.rst
2021-04-02 10:42:15 -06:00
baee023ba2
Update Control_Waveforms3.svg
2021-04-02 10:41:47 -06:00
65d2f82b94
Update Control_Waveforms3.svg
2021-04-02 10:41:29 -06:00
9849946fab
Update Control_Waveforms3.svg
2021-04-02 10:41:12 -06:00
821847f295
Update Control_Waveforms3.svg
2021-04-02 10:40:51 -06:00
96275f9c0e
Modify Control_Waveforms to fix height and width
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The height and width will now be set to the size of the viewbox
2021-04-02 10:39:20 -06:00
69b7c8f37a
Update to include new control_waveforms file
2021-04-02 10:32:31 -06:00
f03754561c
Add control_waveforms with smaller viewbox
2021-04-02 10:27:49 -06:00
c0256cdd87
Adjust height and width to see if image changes
2021-04-02 10:22:09 -06:00
d56ba1c5d7
Modify custom waveform to have a smaller viewbox
2021-04-02 10:13:51 -06:00
1bbf878498
Modify image to have a smaller viewbox
2021-04-02 10:13:13 -06:00
6393d11153
Update to highlight correct section of code
2021-04-02 10:04:53 -06:00
bff9e7aecd
Update hyperlinks to display properly
2021-04-02 10:02:26 -06:00
5f01e5e7a7
Update file
2021-04-02 09:54:54 -06:00
0072f4e51e
Merge branch 'master' into tutorials
2021-03-31 10:31:55 -06:00
c1036c6ac4
Match spelling to file name for cell_libraries
2021-03-31 10:04:51 -06:00
f8da09a80e
Update to include cell_library tutorial
2021-03-31 10:04:00 -06:00
36a6870cc0
Update tutorial to display waveforms
2021-03-30 21:59:18 -06:00
f963be4cae
Add files via upload
2021-03-30 21:56:43 -06:00
b8b024048e
Add first draft for Open Cell Libraries tutorial
2021-03-30 21:54:46 -06:00
eec52360ee
Merge branch 'master' into doc_patch
2021-03-23 21:33:05 -06:00
8ee86d78dd
Implement some of the final changes
2021-03-23 20:50:54 -06:00
16cefdba28
Fix minor changes in page
2021-03-23 18:19:14 -06:00
3dea033981
Implement more code blocks for cleaner page
2021-03-23 18:12:27 -06:00
ccfcae88d7
Update to remove clunky image with code-block
2021-03-23 17:41:55 -06:00
191ce358c7
Indent code-blocks
2021-03-23 17:29:34 -06:00
34a1df858b
Fix code-block syntax for XML
2021-03-23 17:25:32 -06:00
59ecaae23b
Update to use code-block syntax
2021-03-23 17:21:44 -06:00
07f05cc942
Update user_defined_temp_tutorial.rst
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Update to remove two images that were hard to read on the webpage and replace with code blocks
2021-03-23 17:16:27 -06:00
4317f7add7
Update file to display images w/caps
2021-03-23 16:50:52 -06:00
b194e9c395
Update index.rst
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Include link to user_defined_temp_tutorial file
2021-03-23 16:37:44 -06:00
4d0e06c332
Update user_defined_temp_tutorial
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Add more sections, robust instructions, and a link to documentation
2021-03-23 16:34:32 -06:00
a6dfba4500
Update to try and display tutorial images
2021-03-19 16:29:25 -06:00
e90bcdc4d5
Update to correctly include figure syntax
2021-03-19 16:21:45 -06:00
05ec5186a2
Update to see if .. image:: works for images
2021-03-19 16:18:21 -06:00
4e363660e7
Update to correct syntax for images
2021-03-19 16:14:51 -06:00
eea73ca2bf
Add user_defined_templates.rst file
2021-03-19 16:10:46 -06:00
7b23231909
Add images for user_defined_templates.v tutorial
2021-03-19 16:08:50 -06:00
19b2641839
Merge branch 'master' into doc_patch
2021-03-15 11:45:32 -06:00
fb7d76545e
[Doc] Patch the schematic of LUT circuit models to be consistent with netlists
2021-03-15 11:40:09 -06:00
ff0faeb285
[Doc] Update documentation about the extended bitstream setting
2021-03-10 21:41:59 -07:00
c638e5bde5
[Doc] Update documentation for default net type option
2021-02-28 12:00:55 -07:00
01b9bf2a02
[Doc] Update num_region XML for config protocol
2021-02-18 21:58:30 -07:00
2eaec13351
[Doc] Reorganize tutorial documentation by grouping compilation guidelines, shell setup and tool guide into a section
2021-02-11 14:09:20 -07:00
702bd3bbd5
Merge pull request #231 from lnis-uofu/dev
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Extended LUT Support: Now accept external LUT netlists with embedded custom logic
2021-02-11 13:57:17 -07:00
184788880c
Merge pull request #224 from lnis-uofu/gg_docs
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[Docs] Added documentation for docker based run and shell shortcuts documentation
2021-02-11 09:26:29 -07:00
1c4dc9f74b
[Doc] Update documentation about the super LUT feature
2021-02-10 11:49:59 -07:00
c35cf72489
[Docs] Added OpenFPGA shortcut commands docs
2021-02-07 23:53:05 -07:00
cbd2064f59
[Docs] Updated docker based run documentation
2021-02-07 23:33:25 -07:00
9020577e80
Support SVG in Sphinx Latex building ( #220 )
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* [Doc] Try use image converter instead of svg2pdf which requires more dependencies
* [Doc] Add img converter to conf.py
* [Doc] Bug fix in importing imgconverter package
* [Doc] Try to fix the bug when importing python packages
* [Doc] bug fix
* [Doc] Try to use imgconverter rather than cairo
* [Doc] Add svg to latex config in sphinx configuration file
* [Doc] Try cairo svg converter
* [Doc] Correct bugs in compiling latexpdf
* [Doc] Use latest image in building readthedocs
* [Doc] Now use readthedocs docker image in building online documentation
* [Doc] Correct typo in readthedocs setting
* [Doc] Try to use inkscape converter as imgconverter converted SVG to black images
* [Doc] Try RSVG
2021-02-07 18:53:16 -07:00
b71966363b
[Doc] Try RSVG
2021-02-07 18:16:33 -07:00
3c1a538f7a
[Doc] Try to use inkscape converter as imgconverter converted SVG to black images
2021-02-07 17:53:58 -07:00
tangxifan
Ganesh Gore
taoli4rs
Aram Kostanyan
Awais Abbas
nadeemyaseen-rs
ANDREW HARRIS POND
bbleaptrot
Andrew Pond
ganeshgore
Parnabrita Mondal