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[Doc] Update documentation on the WLR definition for circuit model

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tangxifan 2021-09-20 17:21:33 -07:00
parent d36d1ebee2
commit 3146d2484f
2 changed files with 31 additions and 1 deletions
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2
docs/source/manual/arch_lang/circuit_library.rst
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@ -201,7 +201,7 @@ A circuit model may consist of a number of ports. The port list is mandatory in
.. note:: Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of :ref:``circuit_model_example`` for more details.
.. note:: Note that we have a list of reserved port names, which indicate the usage of these ports when building FPGA fabrics. Please do not use ``mem_out``, ``mem_inv``, ``bl``, ``wl``, ``blb``, ``wlb``, ``ccff_head`` and ``ccff_tail``.
.. note:: Note that we have a list of reserved port names, which indicate the usage of these ports when building FPGA fabrics. Please do not use ``mem_out``, ``mem_inv``, ``bl``, ``wl``, ``blb``, ``wlb``, ``wlr``, ``ccff_head`` and ``ccff_tail``.
FPGA I/O Port
^^^^^^^^^^^^^

30
docs/source/manual/arch_lang/circuit_model_examples.rst
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@ -333,6 +333,36 @@ The following XML codes describes the SRAM cell shown in :numref:`fig_sram_blwl`
.. note:: When the ``memory_bank`` type of configuration procotol is specified, SRAM modules should have a BL and a WL.
.. _circuit_model_sram_blwlr_example:
SRAM with BL/WL/WLR
```````````````````
.. _fig_sram_blwlr:
.. figure:: ./figures/sram_blwlr.png
:scale: 100%
An example of a SRAM with Bit-Line (BL) and Word-Line (WL) control signals
The following XML codes describes the SRAM cell shown in :numref:`fig_sram_blwlr`.
.. code-block:: xml
<circuit_model type="sram" name="sram_blwlr" prefix="sram_blwlr" verilog_netlist="sram.v" spice_netlist="sram.sp"/>
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="bl" prefix="bl" size="1"/>
<port type="wl" prefix="wl" size="1"/>
<port type="wlr" prefix="wlr" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="output" prefix="outb" size="1"/>
</circuit_model>
.. note:: OpenFPGA always assume that a ``WL`` port should be the write enable signal, a ``WLR`` port should be the read enable signal, while a ``BL`` port is the data input.
.. note:: When the ``memory_bank`` type of configuration procotol is specified, SRAM modules should have a BL and a WL. WLR is optional
.. _circuit_model_config_latch_example:
Configurable Latch