fix mistake in first line of page

2021-06-16 12:45:04 -06:00 · 2021-06-16 12:45:04 -06:00 · 858bb2f21e
parent 624e9f3bb7
commit 858bb2f21e
1 changed files with 1 additions and 1 deletions
--- a/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst
+++ b/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst
@ -1,4 +1,4 @@
-.. tutorial_user_def_temp:
+.. _tutorial_user_def_temp:

 Integrating Custom Verilog Modules with user_defined_template.v
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