Update tutorial to correctly display code
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@ -10,18 +10,18 @@ Introduction
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- Modify an existing architecture to incorporate Spypads
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- Verify correctness through GTKWave
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Through this tutorial, we will show how to create Spypads in OpenFPGA
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Through this tutorial, we will show how to create Spypads in OpenFPGA.
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Spypads are physical output pins on a FPGA chip through which you can read out internal signals when doing silicon-level debugging. The XML syntax for spypads and other
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global signals can be found on our :ref:`circuit_library` documentation page.
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To create a spypad, the ``port type`` needs to be set to **output** and ``is_global`` and ``is_io`` need to be set to **true**:
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.. code-block:: XML
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.. code-block:: xml
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<port type="output" is_global="true" is_io="true"/>
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When the port is syntactically correct, the outputs are independently wired from different instances to separated FPGA outputs and would physically look like
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:numref:`fig_gpout`:
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When the port is syntactically correct, the outputs are independently wired from different instances to separated FPGA outputs and would physically look like :numref:`fig_gpout`:
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.. _fig_gpout:
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@ -39,13 +39,14 @@ An OpenFPGA architecture file that contains spypads and has a task that referenc
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file. We can view ``k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml`` by entering the following command at the root directory of OpenFPGA:
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.. code-block:: bash
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emacs openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
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The spypads are defined from **LINE181** to **LINE183** and belong to the ``frac_lut6_spypad`` ``circuit_model`` that begins at **LINE172**
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.. code-block:: XML
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.. code-block:: xml
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:emphasize-lines: 10, 11, 12
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<circuit_model type="lut" name="frac_lut6_spypad" prefix="frac_lut6_spypad" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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@ -60,7 +61,7 @@ The spypads are defined from **LINE181** to **LINE183** and belong to the ``frac
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<port type="output" prefix="lut6_out" size="1" lut_output_mask="0" is_global="true" is_io="true"/>
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<port type="sram" prefix="sram" size="64"/>
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
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</circuit_model>
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</circuit_model>
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The spypads are instantiated in the top-level verilog module ``fpga_top.v``. ``fpga_top.v`` is automatically generated when we run our task from the OpenFPGA root
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directory. However, we need to modify the task configuration file to run the **full testbench** instead of the **formal testbench** to view the spypads' waveforms in
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@ -71,6 +72,7 @@ GTKWave.
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To open the task configuration file, run this command from the root directory of OpenFPGA:
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.. code-block:: bash
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emacs openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf
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The last line of the task configuration file (**LINE44**) sets the **formal testbench** to be the desired testbench. To use the **full testbench**, comment out **LINE44**.
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@ -128,6 +130,7 @@ The file will look like this when finished:
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Our OpenFPGA task will now run the full testbench. We run the task with the following command from the root directory of OpenFPGA:
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.. code-block:: bash
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs
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.. note:: Python 3.8 or later is required to run this task
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@ -135,11 +138,13 @@ Our OpenFPGA task will now run the full testbench. We run the task with the foll
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We can now see the instantiation of these spypads in ``fpga_top.v`` and ``luts.v``. We will start by viewing ``luts.v`` with the following command:
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.. code-block:: bash
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emacs openfpga_flow/tasks/fpga_verilog/spypad/latest/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.verilog
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The spypads are coming from the ``frac_lut6_spypad`` circuit model. In ``luts.v``, the ``frac_lut6_spypad`` module is defined around **LINE150** and looks as follows:
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.. code-block:: verilog
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module frac_lut6_spypad(in,
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sram,
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sram_inv,
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@ -168,11 +173,13 @@ The spypads are coming from the ``frac_lut6_spypad`` circuit model. In ``luts.v`
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The ``fpga_top.v`` file has some similarities. We can view the ``fpga_top.v`` file by running the following command:
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.. code-block:: bash
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emacs openfpga_flow/tasks/fpga_verilog/spypad/latest/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/fpga_top.v
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If we look at the module definition and ports of ``fpga_top.v`` we should see the following:
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..code-block:: verilog
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.. code-block:: verilog
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module fpga_top(pReset,
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prog_clk,
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TESTEN,
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@ -223,6 +230,7 @@ Using :numref:`fig_gpout` as a guide, we can relate our task like :numref:`fig_g
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We can view testbench waveforms with GTKWave by running the following command from the root directory:
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.. code-block:: bash
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gtkwave openfpga_flow/tasks/fpga_verilog/spypad/latest/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd &
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.. note::Information on GTKWave can be found on our documentation page located here: :ref:`verilog2verification`
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@ -243,37 +251,44 @@ We will modify the``k6_frac_N10_adder_chain_40nm_openfpga.xml`` file found in Op
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the file by running the following command:
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.. code-block:: bash
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emacs openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
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Replace **LINE214** with the following:
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.. code-block:: xml
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<port type="output" prefix="sumout" lib_name="SUM" size="1" is_global=”true” is_io=”true”/>
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**sumout** is now a global output. **sumout** will show up in the ``fpga_top.v`` file and will have waveforms in GTKWave if we run the **full testbench**. To run the
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**full testbench**, we have to modify the ``hard_adder`` configuration file:
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.. code-block:: bash
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emacs openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf
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Comment out the last line of the file to run the **full testbench**:
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.. code-block:: python
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#vpr_fpga_verilog_formal_verification_top_netlist=
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We now run the task to see our changes:
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.. code-block:: bash
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
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We can view the global ports in ``fpga_top.v`` by running the following command:
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.. code-block:: bash
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emacs openfpga_flow/tasks/fpga_verilog/adder/hard_adder/run064/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/fpga_top.v
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The ``fpga_top.v`` should have the following in its module definition:
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.. code-block:: verilog
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module fpga_top(pReset,
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prog_clk,
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set,
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@ -299,6 +314,7 @@ The ``fpga_top.v`` should have the following in its module definition:
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We can view the waveform by running GTKWave:
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.. code-block:: bash
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gtkwave openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd &
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The waveform should have some changes to its value. An example of what it may look like is displayed in :numref:`fig_spy_adder`
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@ -315,4 +331,4 @@ Conclusion
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In this tutorial, we have shown how to build spypads into OpenFPGA Architectures using XML Syntax. If you have any issues, feel free to `contact`_ us.
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.. _contact: https://openfpga.readthedocs.io/en/master/contact/
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.. _contact: https://openfpga.readthedocs.io/en/master/contact/
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