Add first draft for Open Cell Libraries tutorial
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Using Open-source Cell Libraries with OpenFPGA Architectures
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============================================================
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Introduction
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~~~~~~~~~~~~
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**In this tutorial, we will**
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- Clone the Skywater Processor Development Kit into the OpenFPGA root directory
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- Use Skywater's PDK cell library to create an OR Gate circuit model for OpenFPGA
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- Verify that the cell library file was correctly bound into the selected architecture file by looking at auto-generated OpenFPGA files and checking simulation waveforms in GTKWave
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Through this example, we will show how to bind open-source cell library files with OpenFPGA Architectures.
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Create and Verify the Control Circuit Model
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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For this tutorial, we will first create a control that we will use to compare the final product of this tutorial with. The final product will be an **OR2** circuit model referencing Skywater's PDK cell library.
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To follow along, go to the root directory of OpenFPGA and enter:
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.. code-block:: bash
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python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
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This will run a prebuilt task with OpenFPGA cell libraries. When the task is finished, there will be many auto-generated files to look through. For this tutorial, we are interested
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in the ``luts.v`` and ``and2_formal.vcd`` files. The ``luts.v`` file will eventually have the changes we will implement in the tutorial,
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and the ``and2_formal.vcd`` file will have the resulting waveforms from the simulation run by the task. To open the ``luts.v`` file, run the following command:
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.. code-block:: bash
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vi openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.v
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The ``luts.v`` file represents a Look Up Table within the OpenFPGA architecture. The important lines of this file for the tutorial are **LINE58**, **LINE59**, and **LINE72** to **LINE80**.
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These lines show the instantiation of OpenFPGA's **OR2** cell library.
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**LINE58**:
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.. code-block:: verilog
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wire [0:0] OR2_0_out;
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**LINE59**:
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.. code-block:: verilog
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wire [0:0] OR2_1_out;
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**LINE72** to **LINE80**:
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.. code-block:: verilog
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OR2 OR2_0_ (
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.a(mode[0:0]),
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.b(in[4]),
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.out(OR2_0_out));
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OR2 OR2_1_ (
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.a(mode[1]),
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.b(in[5]),
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.out(OR2_1_out));
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We will also need to look at the control's simulation waveforms. Viewing the waveforms is done through GTKWave with the following command:
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.. code-block:: bash
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gtkwave openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd &
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The simulation waveforms should look similar to the following :numref:`fig_control_output`:
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.. _fig_control_output:
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.. figure:: ./figures/control_output.svg
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:scale: 100%
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Control Circuit Model's Simulation Waveforms
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.. note:: The waveform inputs do not need to exactly match because the testbench provides input in random intervals.
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We have now finished creating the control and viewing the important sections for this tutorial. We can now incorporate Skywater's cell library to create a new circuit model.
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Clone Skywater PDK into OpenFPGA
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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We will be using the open-source Skywater Processor Development Kit to aid us in creating our circuit model. We start by cloning the Skywater PDK github repository into the OpenFPGA root directory.
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Run the following command in the root directory of OpenFPGA:
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.. code-block:: bash
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git clone https://github.com/google/skywater-pdk.git
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Once the repository has been cloned, we need to build the cell libraries by running the following command in the Skywater PDK root directory:
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.. code-block:: bash
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SUBMODULE_VERSION=latest make submodules -j3 || make submodules -j1
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This will take some time to complete due to the size of the libraries. Once the libraries are made, creating the circuit model can begin.
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Create and Verify the Cell Library Circuit Model
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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To create the circuit model, we will modify the ``k6_frac_N10_adder_chain_40nm_openfpga.xml`` OpenFPGA architecture file. We will remove the circuit model
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for OpenFPGA's **OR2** gate, replace the circuit model with one referencing the Skywater cell library, and modify the LUT that references the old **OR2**
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circuit model to reference our new circuit model. We begin by running the following command in the root directory:
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.. code-block:: bash
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vi openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
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We begin the circuit model creation process by replacing **LINE67** to **LINE81** with the following:
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.. code-block:: xml
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<circuit_model type="gate" name="sky130_fd_sc_ls__or2_1" prefix="sky130_fd_sc_ls__or2_1" verilog_netlist="${OPENFPGA_PATH}/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/or2/sky130_fd_sc_ls__or2_1.v">
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<design_technology type="cmos" topology="OR"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="A" size="1"/>
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<port type="input" prefix="B" size="1"/>
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<port type="output" prefix="X" size="1"/>
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</circuit_model>
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.. note:: The name of the circuit model must be consistent with the standard cell!
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The most significant differences from the control in this section are changing the ``name`` and ``prefix`` to match the module name from Skywater's cell library and including a path
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to the verilog file using ``verilog_netlist``. The second change to ``k6_frac_N10_adder_chain_40nm_openfpga.xml`` is at **LINE160**, where we will be replacing the line with the following:
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.. code-block:: xml
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<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="sky130_fd_sc_ls__or2_1"/>
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This change replaces the input of the LUT with our new circuit model. Everything is in place to begin verification.
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Verification begins by running the following command:
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.. code-block:: bash
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python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
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The task may output this error:
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.. code-block:: bash
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ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - iverilog_verification run failed with returncode 1
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ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - command iverilog -o compiled_and2 ./SRC/and2_include_netlists.v -s and2_top_formal_verification_random_tb
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ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - -->>error: Unable to find the root module "and2_top_formal_verification_random_tb" in the Verilog source.
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ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - -->>1 error(s) during elaboration.
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ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Current working directory : OpenFPGA/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/run057/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH
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ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Failed to run iverilog_verification task
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ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Exiting . . . . . .
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ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Failed to execute openfpga flow - 00_and2_MIN_ROUTE_CHAN_WIDTH
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This error has occurred because IVerilog could not find the path to the Skywater PDK Cell Library we have selected. To fix this, we need to go to the
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``iverilog_output.txt`` file found here:
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.. code-block:: bash
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emacs openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/iverilog_output.txt
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Replace all the text within ``iverilog_output.txt`` with the following:
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.. code-block:: bash
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iverilog -o compiled_and2 ./SRC/and2_include_netlists.v -s and2_top_formal_verification_random_tb -I ${OPENFPGA_PATH}/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/or2
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We can now manually rerun IVerilog, a tutorial on manually running IVerilog can be found at our ``From Verilog to Verification``_ tutorial. From the root
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directory, run the following commands:
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.. code-block:: bash
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cd openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/
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source iverilog_output.txt
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vvp compiled_and2
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With IVerilog complete, we can verify the cell library has been bound correctly by viewing the ``luts.v`` file and the waveforms with GTKWave.
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From the root directory, view the ``luts.v`` file with this command:
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.. code-block:: bash
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vi openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.v
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Scrolling through ``luts.v``, this should be present in the file:
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.. code-block:: verilog
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wire [0:0] sky130_fd_sc_ls__or2_1_0_X;
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wire [0:0] sky130_fd_sc_ls__or2_1_1_X;
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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// ----- END Local output short connections -----
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sky130_fd_sc_ls__or2_1 sky130_fd_sc_ls__or2_1_0_ (
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.A(mode[0:0]),
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.B(in[4]),
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.X(sky130_fd_sc_ls__or2_1_0_X));
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sky130_fd_sc_ls__or2_1 sky130_fd_sc_ls__or2_1_1_ (
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.A(mode[1]),
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.B(in[5]),
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.X(sky130_fd_sc_ls__or2_1_1_X));
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We can check the waveforms as well to see if they are similar with the command:
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.. code-block:: bash
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gtkwave openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd &
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The simulation waveforms should look similar to the following :numref:`fig_custom_output`:
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.. _fig_custom_output:
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.. figure:: ./figures/custom_output.svg
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:scale: 100%
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Custom Circuit Model's Simulation Waveforms
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We have now verified that the Skywater PDK Cell Library has been instantiated and bound to the OpenFPGA architecture file. If you have any problems, reach out to us on github.
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.. _From Verilog to Verification: https://openfpga.readthedocs.io/en/master/tutorials/design_flow/verilog2verification/
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