Update to highlight correct section of code

2021-04-02 10:04:53 -06:00 · 2021-04-02 10:04:53 -06:00 · 6393d11153
parent bff9e7aecd
commit 6393d11153
1 changed files with 1 additions and 1 deletions
--- a/docs/source/tutorials/arch_modeling/open_cell_libraries_tutorial.rst
+++ b/docs/source/tutorials/arch_modeling/open_cell_libraries_tutorial.rst
@ -306,7 +306,7 @@ From the root directory, view the ``luts.v`` file with this command:
 Scrolling through ``luts.v``, this should be present in the file:

 .. code-block:: verilog
-  :emphasize-lines: 58,59,72,73,74,75,76,77,78,79,80
+  :emphasize-lines: 64,65,72,73,74,75,76,77,78,79,80
   
   //-------------------------------------------
   //	FPGA Synthesizable Verilog Netlist