[Doc] Update documentation for default net type option

2021-02-28 12:00:55 -07:00 · 2021-02-28 12:00:55 -07:00 · c638e5bde5
parent 15e26a5602
commit c638e5bde5
1 changed files with 4 additions and 0 deletions
--- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
+++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
@ -12,6 +12,10 @@ write_fabric_verilog

    Specify the output directory for the Verilog netlists. For example, ``--file /temp/fabric_netlist/``

+  .. option:: --default_net_type <string>
+
+    Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
+
  .. option:: --explicit_port_mapping

    Use explicit port mapping when writing the Verilog netlists