Update to fix grammar and spelling errors

docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst

@@ -3,18 +3,18 @@ Integrating Custom Verilog Modules with user_defined_template.v
 Introduction and Setup
 ~~~~~~~~~~~~~~~~~~~~~~
 **In this tutorial, we will**
-   - Provide motivation for generating the user_defined_template.v verilog file
+   - Provide the motivation for generating the user_defined_template.v verilog file
    - Go through a generated user_defined_template.v file to demonstrate how to use it
-Through this example, we will motivate and show how to use the ``user_defined_template.v`` file.
+Through this example, we will show how and when to use the ``user_defined_template.v`` file.
 
-For this examaple, we are using a modified version of the hard adder task that comes with OpenFPGA.
+For this example, we are using a modified version of the hard adder task that comes with OpenFPGA.
 To follow along, go to the root directory of OpenFPGA and enter: 
 
 .. code-block:: bash
 
    vi openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml 
 
-Go to **LINE187** and replace it with:
+Go to **LINE187** and replace **LINE187** with:
 
 .. code-block:: XML
 
@@ -22,13 +22,13 @@ Go to **LINE187** and replace it with:
 
 Motivation
 ~~~~~~~~~~
-From the OpenFPGA root directory run the command
+From the OpenFPGA root directory, run the command:
 
 .. code-block:: bash
 
    python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
 
-Running this command should fail and produce these errors:
+Running this command should fail and produce the following errors:
 
 .. code-block:: bash
    
@@ -58,13 +58,13 @@ Running this command should fail and produce these errors:
    ERROR - Current working directory :    /research/ece/lnis/USERS/leaptrot/OpenFPGA/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/run019/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH
    ERROR - Failed to run iverilog_verification task
    ERROR - Exiting . . . . . .
-This error log can be found by running the following command from the root directory:
+This error log can also be found by running the following command from the root directory:
 
 .. code-block:: bash
 
    cat openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/00_and2_MIN_ROUTE_CHAN_WIDTH_out.log
 
-This command failed during the verification step because the path to the module definition for **ADDF** is missing. In our architecture file, user-defined verilog modules are those ``<circuit_model>`` with the key term `verilog_netlist`. The ``user_defined_template.v`` file provides a module template for incorporating Hard IPs with no external library into the architecture. 
+This command failed during the verification step because the path to the module definition for **ADDF** is missing. In our architecture file, user-defined verilog modules are those ``<circuit_model>`` with the key term `verilog_netlist`. The ``user_defined_template.v`` file provides a module template for incorporating Hard IPs without external library into the architecture. 
 
 Fixing the Error
 ~~~~~~~~~~~~~~~~
@@ -80,6 +80,8 @@ Now we can return to the root directory and run this command again:
 .. code-block:: bash
 
    python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
+   
+The task should now complete without any errors.
 
 Fixing the Error with user_defined_template.v
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -89,7 +91,7 @@ The `user_defined_template.v`_ file can be found starting from the root director
 
    vi openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/user_defined_template.v
 
-.. note:: This file contains user-defined verilog modules that are found in the openfpga_cell_library with ports declaration (compatible with other netlists that are auto-generated by OpenFPGA) but without functionality. The file is used as a reference for engineers to check what is the port sequence required by top-level verilog netlists. This file can be included in simulation only if there are modifications to the file.
+.. note:: The ``user_defined_template.v`` file contains user-defined verilog modules that are found in the openfpga_cell_library with ports declaration (compatible with other netlists that are auto-generated by OpenFPGA) but without functionality. ``user_defined_template.v`` is used as a reference for engineers to check what is the port sequence required by top-level verilog netlists. ``user_defined_template.v`` can be included in simulation only if there are modifications to the ``user_defined_template.v``.
 
 To implement our own **ADDF** module, we need to remove all other module definitions (they are already defined elsewhere and will cause an error if left in). Replace the ``user_defined_template.v`` file with the following: