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[Doc] Update documentation about time unit support in writing simulation file

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tangxifan 2021-06-25 10:34:43 -06:00
parent 2bb514c51a
commit 507f5ee54c
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docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
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@ -177,6 +177,10 @@ write_simulation_task_info
Specify the type of testbenches [``preconfigured_testbench``|``full_testbench``]. By default, it is the ``preconfigured_testbench``.
.. option:: --time_unit <string>
Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``ms``).
.. option:: --verbose
Show verbose log