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OpenFPGA
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218 Commits

Author SHA1 Message Date
tangxifan edfe3144c3 update profiling, found where runtime is lost 2019-07-09 20:28:01 -06:00
tangxifan 737cc2874f Merge branch 'tileable_routing' into dev 2019-07-09 17:42:44 -06:00
tangxifan 65f696c1d7 fix critical bugs in rectangle floorplan 2019-07-09 17:41:20 -06:00
Baudouin Chauviere 4ca0967453 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-09 14:35:51 -06:00
Baudouin Chauviere 792ba23f4f Correction pre-merge 2019-07-09 14:34:34 -06:00
Baudouin Chauviere 589f58b55e Regression test succeeded 2019-07-09 09:18:06 -06:00
Baudouin Chauviere 25f5bc7792 Latest version, not stable yet but close 2019-07-09 08:34:01 -06:00
tangxifan 5d5e09fcdb minor fix in trying to accelerate the unique routing functions 2019-07-08 17:12:36 -06:00
Baudouin Chauviere df0a3d23a3 Correction top module 2019-07-08 10:23:14 -06:00
Baudouin Chauviere ae05c553d5 Top module done 2019-07-08 09:48:33 -06:00
tangxifan d64aeef5c4 add profiling to routing compact process 2019-07-03 16:57:34 -06:00
tangxifan 1a1da30ae9 fixed a critical bug in using tileable route chan W 2019-07-03 16:46:43 -06:00
tangxifan b79d276ea9 add profiling to fpga_x2p_setup 2019-07-03 14:44:54 -06:00
tangxifan 02398818a9 update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area 2019-07-03 10:33:02 -06:00
Baudouin Chauviere b08513d902 Big chunk added on the routing part of the explicit mapping 2019-07-02 14:12:42 -06:00
Baudouin Chauviere 8f5ad2eb67 Snapshot of progress 2019-07-02 10:10:48 -06:00
tangxifan 95674c4687 added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
tangxifan 44301bfd77 updated SPICE generator to avoid issues on clb2clb_direct 2019-07-02 09:01:52 -06:00
tangxifan 5b25bbb120 bug fixed for direct connection in CBs and direct connection in top netlist 2019-07-01 17:25:00 -06:00
Baudouin Chauviere f189ef1d8f Done with the submodules 2019-07-01 14:24:09 -06:00
Baudouin Chauviere 370ce23646 Mux explicit verilog done 2019-07-01 13:58:24 -06:00
Baudouin Chauviere 863e8677c0 Further add new functions to tree 2019-07-01 12:12:36 -06:00
Baudouin Chauviere 0e04b88c8f Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
Baudouin Chauviere 04eb6d3488 Correction pre-merge 2019-06-27 14:33:06 -06:00
Baudouin Chauviere 7c742f1cbb Stable, is_explicit propagated through the code. Not implemented though except for muxes 2019-06-27 10:29:57 -06:00
tangxifan 8edd85c9fc keep fixing bugs in verilog SDC generator for tileable CBs 2019-06-26 22:58:52 -06:00
tangxifan 711e369fe7 fixing bugs in the SDC generator and report_timing 2019-06-26 18:09:09 -06:00
tangxifan 0fe54d87d5 fixed a bug in SDC generator for constraining SBs in tileable arch 2019-06-26 17:06:14 -06:00
Baudouin Chauviere 0ce9846e47 Stable, unfinished 2019-06-26 16:54:41 -06:00
tangxifan 7d85eb544d start fixing bugs for SDC generator when using tileable arch 2019-06-26 16:48:17 -06:00
tangxifan f5920c7422 fix bugs in ptc_num using for SB 2019-06-26 16:21:02 -06:00
tangxifan 3d8200e217 critical bug fixed in bitstream generator for compact routing hierarchy 2019-06-26 15:51:11 -06:00
tangxifan d2ed82d14d Merge branch 'tileable_routing' into multimode_clb 2019-06-26 15:00:39 -06:00
tangxifan 57616361c2 fixed critical bugs in cb configuration port indices 2019-06-26 14:58:52 -06:00
Baudouin Chauviere d2bd2be76b Warnings correction in the make sequence 2019-06-26 14:33:12 -06:00
Baudouin Chauviere 87ddca9f57 commiting current work. Stable but function not implemented yet 2019-06-26 14:22:02 -06:00
tangxifan 42f85004b6 fix bugs in finding the ending SB of a rr_node 2019-06-26 14:13:41 -06:00
tangxifan 9b6a4b39bb Merge branch 'tileable_routing' into multimode_clb 2019-06-26 11:36:08 -06:00
tangxifan c879e7f6c5 fixed a critical bug when instanciating Connection blocks 2019-06-26 11:33:02 -06:00
Baudouin Chauviere b7c2954b91 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-26 10:51:55 -06:00
Baudouin Chauviere 8f21a3b177 Memory leakage correction 2019-06-26 10:50:38 -06:00
tangxifan d50fb7ee19 fixed the bug in determine passing wires for rr_gsb 2019-06-26 10:50:23 -06:00
AurelienUoU ec504049ef Update Testbenches to increase accuracy + commented compact routing option until debug 2019-06-26 10:01:12 -06:00
tangxifan a3670bb752 Merge branch 'multimode_clb' into tileable_routing 2019-06-26 09:45:04 -06:00
Baudouin Chauviere 56557b94e7 Bug Fix 2019-06-26 08:53:46 -06:00
tangxifan 3c0ef2067d fixed critical bugs in pass_tracks identification and update regression test for tileable arch 2019-06-25 21:59:38 -06:00
Baudouin Chauviere bb250ddef9 Bug fix in cpp 2019-06-25 16:47:10 -06:00
tangxifan 4d3b5f12b4 fixed bugs for UNIVERSAL and WILTON switch blocks 2019-06-25 14:15:29 -06:00
Baudouin Chauviere 332ce17f03 Division between horizontal and vertical analysis 2019-06-25 13:44:41 -06:00
tangxifan a88263a4c2 update rr_block writer to include IPINs in XML files 2019-06-25 11:17:22 -06:00
tangxifan 785b560bd5 sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now 2019-06-24 22:46:56 -06:00
tangxifan fd301eeb66 many bug fixing and now start improving the routability of tileable rr_graph 2019-06-24 17:33:29 -06:00
tangxifan 0d62661c71 bug fixing and spot critical bugs in directlist parser 2019-06-23 20:52:38 -06:00
tangxifan 7c38b32eb1 keep bug fixing for tileable rr_graph generator 2019-06-21 22:51:11 -06:00
tangxifan 1b91c32121 Merge branch 'multimode_clb' into tileable_routing 2019-06-21 17:59:55 -06:00
AurelienUoU 0a42f6a796 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-21 15:47:14 -06:00
AurelienUoU c0d7099cd6 Allow CB on top of blocks with height > 1 2019-06-21 15:46:05 -06:00
tangxifan cf82d87e11 Merge branch 'multimode_clb' into tileable_routing 2019-06-20 18:18:20 -06:00
tangxifan baab9c4a21 basically finished the coding of tileable rr_graph generator. testing to go 2019-06-20 18:17:07 -06:00
Baudouin Chauviere be25b6dd66 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-20 14:11:03 -06:00
Baudouin Chauviere 3bd6c40a10 Report timing modified to have only one liners 2019-06-20 14:10:39 -06:00
AurelienUoU a7502bb43b Avoid configuration bits for module wihch don't require them 2019-06-20 09:40:41 -06:00
tangxifan 2f15d2d13c keep developing tileable rr_graph, track2ipin and opin2track to go 2019-06-19 21:30:16 -06:00
Baudouin Chauviere 57a4ad1f99 Break memories even in the clb sdc 2019-06-16 14:27:29 -06:00
tangxifan c8bf456097 bug fixing for memory leaking in allocating pb_rr_graph and power estimation 2019-06-15 12:23:36 -06:00
tangxifan 4d2a3680be support bus explicit port mapping to standard cells (for BRAMs) 2019-06-14 11:09:15 -06:00
tangxifan 0902d1e75a c++ string is not working, use char which is stable 2019-06-13 18:38:46 -06:00
tangxifan af1628abfe use bus port for primitives in Verilog generator 2019-06-13 16:26:58 -06:00
tangxifan dddbbac85c merge from multimode_clb bug fixing 2019-06-13 15:59:34 -06:00
tangxifan 43128ad3f0 fix a bug in formal verification port for memory bank configuration circuits 2019-06-13 15:33:13 -06:00
tangxifan 44d21ebb90 fixed a bug in Verilog generator supporting SRAM5T 2019-06-13 14:42:39 -06:00
tangxifan 5ae4dec0af fix bugs in CMakeList on enable/disable VPR Graphics 2019-06-12 22:48:00 -06:00
tangxifan 7245917b9c fix a bug for iopad SPICE generation 2019-06-11 11:43:56 -06:00
tangxifan 1776ae3ec8 add explicit port mapping for inverters of memory decoders 2019-06-10 17:36:14 -06:00
tangxifan 8e3ad675e0 use sstream for rr_block verilog writer 2019-06-10 16:23:35 -06:00
tangxifan 009e5244d3 minor fix on the port direction of configuration peripherals for memory decoders 2019-06-10 15:39:35 -06:00
tangxifan f43955037c remove input port requirements for SRAM circuit module 2019-06-10 15:29:44 -06:00
tangxifan e4f70771a2 updated SDC generator to embrace the RRGSB data structure 2019-06-10 14:47:27 -06:00
tangxifan 8a8f4153ce use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB 2019-06-10 12:50:10 -06:00
tangxifan e31407f693 start cleaning up SDC generator with new RRGSB data structure 2019-06-10 10:57:26 -06:00
tangxifan 17bc7fc296 update Verilog generator to use GSB data structure. SDC generator and TCL generator to go 2019-06-08 20:11:22 -06:00
Xifan Tang 61e359efc5 Enable an option to disable/enable graphics in VPR compilation 2019-06-08 15:08:17 -06:00
tangxifan 8c5ec4572d revert string to sprintf 2019-06-07 20:20:41 -06:00
tangxifan 0f1ed19ad0 Revert to the use of sprintf instead std::string. Have no idea why string is not working 2019-06-07 18:54:57 -06:00
tangxifan 44ce0e8834 update gsb unique module detection and fix formal verification port direction 2019-06-07 17:18:38 -06:00
tangxifan 24d53390d8 clean up DeviceRRGSB internal data and member functions 2019-06-07 14:45:56 -06:00
tangxifan c9f810ceb6 update rr_gsb to build connection blocks 2019-06-07 11:01:55 -06:00
tangxifan 472aff5acb add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB 2019-06-06 23:45:21 -06:00
tangxifan ce9fc5696c rename rr_switch_block to rr_gsb, a generic block 2019-06-06 17:41:01 -06:00
tangxifan 8c1e7b799f fixed critical bugs in Connection Block Unique Module detection 2019-06-06 16:31:50 -06:00
tangxifan 873e4d989f fine-tuning Verilog format and node addition to rr_blocks 2019-06-06 12:48:41 -06:00
tangxifan c2de0eefb1 fix redundant comma in SB Verilog module 2019-06-06 09:15:05 -06:00
tangxifan b9e1b1afc4 fix a critical bug in num_reserved_sram_ports 2019-06-05 17:31:01 -06:00
tangxifan aaf8d23971 fix critical bugs in routing submodules 2019-06-05 16:43:18 -06:00
tangxifan 01e075377d fix typo in Verilog generation 2019-06-05 15:30:34 -06:00
tangxifan 21d0cb52bc Merge remote-tracking branch 'origin' into tileable_sb 2019-06-05 13:31:49 -06:00
tangxifan 24ca3104b0 fix minor bugs in Switch Block submodules 2019-06-05 13:30:55 -06:00
tangxifan 0f87ae9886 support switch block submodule Verilog generation by segments 2019-06-05 12:56:05 -06:00
AurelienUoU 84fabbd43b Fix sdc analysis bug related to virtual nodes + add the option in regression test 2019-06-05 12:10:28 -06:00
Baudouin Chauviere d24488092d Fix bug 2019-06-05 11:40:04 -06:00