tangxifan
|
2daa770319
|
[Arch] Update openfpga architecture to include quicklogic cell sim
|
2021-03-08 21:40:29 -07:00 |
|
tangxifan
|
812d8c950e
|
[Script] Update quicklogic's script to output correct verilog file name
|
2021-03-08 21:39:44 -07:00 |
|
tangxifan
|
37aa42d305
|
[Test] Patch task configuration file for lut_adder_test to use correct rewrite script
|
2021-03-08 21:38:51 -07:00 |
|
tangxifan
|
c53c41b7a5
|
[Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file
|
2021-03-08 21:09:23 -07:00 |
|
tangxifan
|
131643dcc0
|
[Flow] Bug fix for yosys rewrite function in openfpga flow-run script
|
2021-03-08 21:08:55 -07:00 |
ganeshgore
|
b860722893
|
Fixed parameter ys_rewrite_params name bug
|
2021-03-08 10:34:39 -07:00 |
|
ganeshgore
|
52de55e7eb
|
Merge branch 'master' into ganesh_dev
|
2021-03-08 10:15:06 -07:00 |
|
tangxifan
|
906d2fa72d
|
Merge branch 'master' into shift_reg
|
2021-03-08 09:24:29 -07:00 |
|
Ganesh Gore
|
7a35811430
|
[Flow] Yosys rewrite support
|
2021-03-08 00:35:47 -07:00 |
|
Ganesh Gore
|
67cd9a69b7
|
[Flow] Extended yosys variable subtitution
|
2021-03-08 00:21:07 -07:00 |
Lalit Sharma
|
7945628307
|
Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification
|
2021-03-07 22:25:01 -08:00 |
|
Lalit Sharma
|
6a1ce01084
|
Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
|
2021-03-07 22:02:11 -08:00 |
Tarachand Pagarani
|
ce76c58422
|
add shift register test case
|
2021-03-05 09:06:05 -08:00 |
|
Lalit Sharma
|
2b2acae757
|
Adding command to generate verilog file out of yosys run
|
2021-03-05 04:07:02 -08:00 |
|
Lalit Sharma
|
0cbad747a1
|
Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
|
2021-03-04 01:10:47 -08:00 |
|
Lalit Sharma
|
817729ac86
|
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
|
2021-03-01 22:31:15 -08:00 |
|
tangxifan
|
e34380a654
|
Merge branch 'master' into default_net_type
|
2021-03-01 08:38:58 -07:00 |
|
Lalit Sharma
|
ea4aee8cb2
|
For time-being yosys script running in no_adder mode.
|
2021-02-28 22:07:23 -08:00 |
|
Lalit Sharma
|
0038496d9c
|
Replacing -openfpga with -family qlf_k4n8
|
2021-02-28 21:08:47 -08:00 |
|
tangxifan
|
b4b6ada06f
|
[Script] Correct bugs in example scripts using default_net_type
|
2021-02-28 16:31:44 -07:00 |
|
tangxifan
|
86930d63d3
|
[Test] Deploy new test to CI
|
2021-02-28 16:18:46 -07:00 |
|
tangxifan
|
b90a17543d
|
[Test] Add new test case to test default nettype in different verilog syntax
|
2021-02-28 16:16:45 -07:00 |
|
tangxifan
|
9f4d05da67
|
[Test] Bug fix for new test case
|
2021-02-28 16:11:30 -07:00 |
|
tangxifan
|
8cc2c7d924
|
[Script] Bug fix for default net type example script
|
2021-02-28 12:35:44 -07:00 |
|
tangxifan
|
6d419fed41
|
[Test] Deploy verilog default net wire type test case to CI
|
2021-02-28 12:33:48 -07:00 |
|
tangxifan
|
18a7041424
|
[Test] Add default net type test for explicit port mapping
|
2021-02-28 12:31:32 -07:00 |
|
tangxifan
|
0723b79bce
|
[Script] Add example script for verilog default net type
|
2021-02-28 12:29:56 -07:00 |
|
tangxifan
|
27200e3daa
|
[Test] Update regression test cases for fpga verilog
|
2021-02-28 12:24:36 -07:00 |
|
tangxifan
|
ff29cc3dff
|
[Test] Move tests to a test group
|
2021-02-28 12:23:35 -07:00 |
|
tangxifan
|
9cb1ca42fe
|
[Test] Deploy default net type option to test case
|
2021-02-28 12:20:43 -07:00 |
|
tangxifan
|
ae05871b1f
|
[Script] Remove default net type from an example script; Limit it to some test cases
|
2021-02-28 12:19:14 -07:00 |
|
tangxifan
|
d7eb159726
|
[Script] Add default net type option to example openfpga shell scripts
|
2021-02-28 12:08:30 -07:00 |
|
tangxifan
|
0d82e4939c
|
[Test] Use unified quicklogic synthesis script and enable end-of-flow tests
|
2021-02-26 09:35:40 -07:00 |
|
tangxifan
|
744d87cb4e
|
[Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues
|
2021-02-26 09:34:52 -07:00 |
|
tangxifan
|
870d3a0e27
|
Merge branch 'master' into dev
|
2021-02-26 09:28:42 -07:00 |
|
Lalit Sharma
|
1082d3c677
|
Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
|
2021-02-25 23:39:07 -08:00 |
|
Lalit Sharma
|
1e48d4f6dc
|
Modifying custom yosys script file name
|
2021-02-25 22:21:39 -08:00 |
|
tangxifan
|
4c2a88e27f
|
[Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed
|
2021-02-24 11:51:10 -07:00 |
|
tangxifan
|
0ce9b66c75
|
[Arch] Add a dummy adder lut circuit model to support HDL simulation
|
2021-02-24 10:09:44 -07:00 |
|
tangxifan
|
86a602d381
|
[Test] Deploy new test to CI
|
2021-02-23 19:55:07 -07:00 |
|
tangxifan
|
a62786986b
|
[Test] Turn off verification in adder lut test temporarily
|
2021-02-23 19:03:25 -07:00 |
|
tangxifan
|
ad25944e59
|
[Arch] Patched superLUT architecture example when trying adder8 synthesis script
|
2021-02-23 19:00:27 -07:00 |
|
tangxifan
|
53df7f69e7
|
[Test] Bug fix in the test case using lut adder
|
2021-02-23 16:59:46 -07:00 |
|
tangxifan
|
db71cc8a16
|
[Test] Add LUT adder test using quicklogic synthesis script
|
2021-02-23 16:50:58 -07:00 |
|
tangxifan
|
19f6b221b1
|
[Test] Rework comments on runtime
|
2021-02-22 15:25:57 -07:00 |
|
tangxifan
|
4803b0ce42
|
[Test] Add test case for sdc controller
|
2021-02-22 15:02:14 -07:00 |
|
tangxifan
|
c7a9a4e896
|
[Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs
|
2021-02-22 15:01:50 -07:00 |
|
tangxifan
|
ca135f3325
|
[Arch] Add flagship architecture with 8-clock
|
2021-02-22 15:01:18 -07:00 |
|
tangxifan
|
2e2b1cb6e7
|
[Test] Use hetergenenous FPGA architecture in quicklogic tests
|
2021-02-22 13:41:04 -07:00 |
|
tangxifan
|
1c09c55e9f
|
[Arch] Add hetergenenous 8-clock FPGA architecture
|
2021-02-22 13:38:50 -07:00 |
|
tangxifan
|
b3fed683f9
|
[Test] Deploy test to CI
|
2021-02-22 12:43:30 -07:00 |
|
tangxifan
|
bc30f62c5a
|
[Test] Add test for sdc controller
|
2021-02-22 12:41:53 -07:00 |
|
tangxifan
|
60dc194d8f
|
[Test] Bug fix in the 5clock test case
|
2021-02-22 11:46:23 -07:00 |
|
tangxifan
|
71e0026a50
|
[Test] Add new test for 5-clock counter to quicklogic tests
|
2021-02-22 11:32:17 -07:00 |
|
tangxifan
|
2bb588dacf
|
[Flow] Add a new script for generating bitstream for multi-clock architectures
|
2021-02-22 11:31:24 -07:00 |
|
tangxifan
|
77896379e2
|
[Arch] Add simulation setting for 8-clock architectures
|
2021-02-22 11:10:03 -07:00 |
|
tangxifan
|
16debe49f6
|
[Arch] Add more comments on the 4 clock simulation setting file
|
2021-02-22 11:04:34 -07:00 |
|
tangxifan
|
0ac75723af
|
[Arch] Add new architecture with 8 clocks
|
2021-02-22 11:00:45 -07:00 |
|
tangxifan
|
b9c2564a7e
|
[Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks
|
2021-02-22 10:49:21 -07:00 |
|
tangxifan
|
bc8aa0ebc6
|
[Test] Remove routing test from quicklogic's flow test
|
2021-02-22 10:22:47 -07:00 |
|
tangxifan
|
2dbdc2644f
|
[Benchmark] Remove replicate micro benchmarks
|
2021-02-22 10:22:19 -07:00 |
|
tangxifan
|
9b6b2068ee
|
[Test] Move MCNC test to benchmark sweep test group
|
2021-02-22 10:18:34 -07:00 |
|
tangxifan
|
c1f4a434e4
|
[Doc] Update README for the regression test tasks
|
2021-02-22 10:17:02 -07:00 |
|
tangxifan
|
d6a02a985e
|
Merge pull request #248 from lnis-uofu/add_quicklogic_tests
Disabling verilog testbench generation for quicklogic tests
|
2021-02-22 09:02:29 -07:00 |
|
Lalit Sharma
|
d842026672
|
Disabling verilog testbench generation for quicklogic tests
|
2021-02-21 21:58:23 -08:00 |
Lalit Narain Sharma
|
be5e0cdea9
|
Merge pull request #241 from lnis-uofu/add_quicklogic_tests
Adding quicklogic tests and updating the corresponding conf file to r…
|
2021-02-22 09:50:26 +05:30 |
|
Lalit Sharma
|
576e6753f6
|
Removing 2 more tests which are variant of and design
|
2021-02-19 09:11:19 -08:00 |
|
Lalit Sharma
|
d4c5a5655a
|
Removing blif file as well as and2 testcase
|
2021-02-19 08:55:17 -08:00 |
|
Lalit Sharma
|
6de0954ca5
|
Uncommenting all benchmarks except 2 that requires multiple clocks
|
2021-02-19 08:40:26 -08:00 |
|
tangxifan
|
e08ac1a41e
|
[Test] Deploy synthesizable verilog test to CI
|
2021-02-18 19:37:45 -07:00 |
|
tangxifan
|
e19fc15fec
|
[Test] bug fix in test case
|
2021-02-18 19:37:45 -07:00 |
|
tangxifan
|
affc8cbbc4
|
[Test] Deploy test to CI
|
2021-02-18 19:37:45 -07:00 |
|
tangxifan
|
2e88b035ed
|
[Test] Add wire LUT repacker test case
|
2021-02-18 19:37:44 -07:00 |
|
tangxifan
|
1f097abe99
|
[Benchmark] Add micro benchmark for FIR filter
|
2021-02-18 19:37:44 -07:00 |
|
Lalit Sharma
|
69cdc11ea5
|
Uncommenting the tests that are running fine
|
2021-02-18 04:17:12 -08:00 |
|
tangxifan
|
d85d6e964e
|
Merge pull request #227 from watcag/master
Standard-cell flow
|
2021-02-17 10:11:34 -07:00 |
|
Lalit Sharma
|
7ee01711c2
|
Merge remote-tracking branch 'origin/master' into add_quicklogic_tests
|
2021-02-17 00:06:59 -08:00 |
|
Lalit Sharma
|
44a979288b
|
Adding quicklogic tests and updating the corresponding conf file to run them
|
2021-02-16 23:08:38 -08:00 |
|
tangxifan
|
a819375f69
|
[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
|
2021-02-16 16:53:13 -07:00 |
|
tangxifan
|
2c2e493739
|
[Test] Remove quicklogic test from basic tests
|
2021-02-16 12:29:10 -07:00 |
|
tangxifan
|
9c19e2b365
|
[Test] Move regression test scripts from workflow to openfpga_flow
|
2021-02-16 11:55:47 -07:00 |
|
Tarachand Pagarani
|
426b6449d8
|
change the test to turn off power analysis
|
2021-02-15 02:45:38 -08:00 |
|
Tarachand Pagarani
|
3a587f663a
|
copy yosys output file in case power analysis setting is off
|
2021-02-15 02:36:02 -08:00 |
|
tangxifan
|
e683e00032
|
[HDL] Add disclaimer for the frac_lut4_arith HDL codes
|
2021-02-10 14:50:11 -07:00 |
|
tangxifan
|
9b86f3bb85
|
Merge branch 'master' into dev
|
2021-02-09 22:40:45 -07:00 |
|
tangxifan
|
22e675148e
|
[HDL] Add HDL codes for a super LUT with embedded carry logic
|
2021-02-09 21:13:22 -07:00 |
|
tangxifan
|
b81b74aa7c
|
[Arch] Patch architecture to support superLUT-related XML syntax
|
2021-02-09 20:23:32 -07:00 |
|
tangxifan
|
7dcc14d73f
|
[Arch] Bug fix in the example arch with super LUT
|
2021-02-09 15:52:22 -07:00 |
|
tangxifan
|
3ae501a5ea
|
[Test] Update test case to use dedicated eblif file
|
2021-02-09 15:51:57 -07:00 |
|
tangxifan
|
1712ee4edb
|
[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture
|
2021-02-09 15:41:21 -07:00 |
Nachiket Kapre
|
4c7f4bd82f
|
ahoy nice
|
2021-02-09 17:38:19 -05:00 |
|
tangxifan
|
2b51b36dd6
|
[Test] Now use the super LUT arch in the test case
|
2021-02-09 15:27:44 -07:00 |
|
tangxifan
|
56284059de
|
[Test] Add a test case for a super LUT
|
2021-02-09 15:25:32 -07:00 |
|
tangxifan
|
304b26c97f
|
[Arch] Add example architectures for superLUT circuit model
|
2021-02-09 15:11:12 -07:00 |
|
Nachiket Kapre
|
71c76df063
|
default to ns for time unit -- synopsys dc whines
|
2021-02-09 17:08:38 -05:00 |
|
Nachiket Kapre
|
6bb2e29f17
|
default to ns for time unit -- synopsys dc whines
|
2021-02-09 17:04:52 -05:00 |
|
Nachiket Kapre
|
87c69460df
|
what is going on
|
2021-02-09 11:33:08 -05:00 |
|
Nachiket Kapre
|
cc74c6268a
|
trying fix chan width
|
2021-02-09 11:28:19 -05:00 |
|
Nachiket Kapre
|
95fe4d7dae
|
adding dff synth
|
2021-02-09 10:34:54 -05:00 |
|
Nachiket Kapre
|
b14b5f975d
|
adding sweep for W
|
2021-02-09 08:48:25 -05:00 |