Claire Wolf
1f4e452609
Run bison with -Wall for verilog front-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:49:36 +02:00
Kamil Rakoczy
02c071888b
Add missing semicolons
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-15 10:15:13 +02:00
Kamil Rakoczy
d77b3305d8
Fix S/R conflicts
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This commit fixes S/R conflicts introduced by commit 6f9be93
.
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-10 15:03:53 +02:00
Kamil Rakoczy
0ffaddee5e
Fix R/R conflicts
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This commit fixes R/R conflicts introduced by commit 7e83a51
.
Parameter logic is already defined as part of `param_range_type` rule.
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-10 15:03:01 +02:00
Kamil Rakoczy
de649b9194
Revert "Revert PRs #2203 and #2244."
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This reverts commit 9c120b89ac
.
2020-07-10 09:59:48 +02:00
whitequark
dc35ef05f9
verilog_parser: turn S/R and R/R conflicts into hard errors.
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Fixes #2253 .
2020-07-09 19:36:59 +00:00
whitequark
9c120b89ac
Revert PRs #2203 and #2244 .
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This reverts commit 7e83a51fc9
.
This reverts commit b422f2e4d0
.
This reverts commit 7cb56f34b0
.
This reverts commit 6f9be939bd
.
This reverts commit 76a34dc5f3
.
2020-07-09 19:36:32 +00:00
Lukasz Dalek
7e83a51fc9
Support logic typed parameters
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-07-06 09:18:48 +02:00
clairexen
7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar
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Signed and macro grammar update
2020-07-01 16:41:32 +02:00
clairexen
8ce4f8790e
Merge pull request #2179 from splhack/static-cast
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Support SystemVerilog Static Cast
2020-07-01 16:40:20 +02:00
Lukasz Dalek
6f9be939bd
Parse macro call attached semicolon as empty expression
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-26 15:38:20 +02:00
Lukasz Dalek
7cb56f34b0
Fix integer signing grammar
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This commit fixes signed/unsigned grammar in parameters as defined in SV
LRM A2.2.1. Example of correct parameters:
parameter integer signed i = 0;
parameter integer unsigned i = 0;
Example of incorrect parameters:
parameter signed integer i = 0;
parameter unsigned integer i = 0;
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-26 15:35:56 +02:00
whitequark
12c016ebdc
Merge pull request #2188 from antmicro/missing-operators
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Add logic-assignments operators
2020-06-26 07:30:27 +00:00
Kamil Rakoczy
539087f417
Support missing sub-assign and and-assign operators
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-25 13:29:06 +02:00
Lukasz Dalek
a4b4c22c96
Support missing xor-assign operator
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 14:32:12 +02:00
Lukasz Dalek
a8750b496e
Support optional labels at the end of package definition
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 11:57:45 +02:00
Lukasz Dalek
3b81a1b809
Support optional labels at the end of module definition
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 11:57:45 +02:00
Kamil Rakoczy
22408f24c7
Add plus-assignment operator
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:54:30 +02:00
Kamil Rakoczy
416a66aee8
Add or-assignment operator
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:53:50 +02:00
Kazuki Sakamoto
185bbbe681
static cast: support changing size and signedness
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Support SystemVerilog Static Cast
- size
- signedness
- (type is not supposted yet)
Fix #535
2020-06-19 17:39:20 -07:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Anonymous Maarten
504f220619
MSVC does not understand __builtin_unreachable
2020-06-17 15:10:08 +02:00
Anonymous Maarten
35008e6d40
MSVC cannot omit operand in conditional
2020-06-17 15:10:08 +02:00
Peter Crozier
76c499db71
Support packed arrays in struct/union.
2020-06-07 18:33:11 +01:00
Peter Crozier
0d3f7ea011
Merge branch 'master' into struct
2020-06-03 17:19:28 +01:00
whitequark
2116d9500c
Merge pull request #2033 from boqwxp/cleanup-verilog-lexer
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verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
2020-05-29 06:46:33 +00:00
Rupert Swarbrick
6aa0f72ae9
Silence spurious warning in Verilog lexer when compiling with GCC
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The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.
2020-05-26 17:54:57 +01:00
Eddie Hung
c5a9abba11
verilog: move attr from simple_behav_stmt to its children to attach
2020-05-25 07:36:53 -07:00
Eddie Hung
1c117ac023
verilog: do not warn for attributes on null statements
2020-05-25 07:36:53 -07:00
Eddie Hung
88bddb37c9
verilog: handle empty generate statement by removing gen_stmt_or_null...
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... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.
2020-05-25 07:36:53 -07:00
Eddie Hung
d21a07c7b5
verilog: fix #2037 by permitting (and freeing) attributes on null stmt
2020-05-25 07:36:53 -07:00
Eddie Hung
574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
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verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
2020-05-21 11:00:36 -07:00
Eddie Hung
38e858af8d
Update frontends/verilog/verilog_parser.y
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Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-05-21 09:10:56 -07:00
Eddie Hung
7101ef550b
verilog: attributes before task enable (but 13 s/r conflicts)
2020-05-14 16:10:11 -07:00
Eddie Hung
237962debd
verilog: default to input in sv mode if task/func has no dir ...
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otherwise error
2020-05-13 13:33:37 -07:00
Peter Crozier
17f050d3c6
Allow structs within structs.
2020-05-12 17:20:34 +01:00
Peter Crozier
f482c9c016
Generalise structs and add support for packed unions.
2020-05-12 14:25:33 +01:00
Eddie Hung
1f3003be7d
verilog: error out when non-ANSI task/func arguments
2020-05-11 13:00:36 -07:00
Peter Crozier
0b6b47ca67
Implement SV structs.
2020-05-08 14:40:49 +01:00
Claire Wolf
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
Eddie Hung
a299e606f8
Merge pull request #2028 from zachjs/master
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verilog: allow null gen-if then block
2020-05-06 12:10:28 -07:00
Zachary Snow
8f9bba1bbf
verilog: allow null gen-if then block
2020-05-06 08:43:02 -04:00
Alberto Gonzalez
323aa1df75
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
2020-05-06 07:22:17 +00:00
Eddie Hung
283b1130a6
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup
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frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-05 07:59:40 -07:00
Eddie Hung
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
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verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
Eddie Hung
eb5eb60fd4
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
Eddie Hung
22bf22fab4
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
Eddie Hung
eca9fc01a7
verilog: set src attribute for primitives
2020-05-04 10:22:05 -07:00
Claire Wolf
589ed2d970
Add AST_SELFSZ and improve handling of bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Alberto Gonzalez
00d74f0b9c
Set Verilog source location for explicit blocks (`begin` ... `end`).
2020-04-17 06:23:03 +00:00
Alberto Gonzalez
10a814f978
Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.
2020-04-17 06:16:59 +00:00
Alberto Gonzalez
9253497358
Add location information to `AST_CONSTANT` nodes.
2020-04-16 19:11:47 +00:00
whitequark
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl
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support using previously declared types/localparams/parameters in package
2020-04-14 12:40:00 +00:00
David Shah
0a178de1b3
verilog: Fix write to deleted object
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-12 18:49:09 +01:00
Jeff Wang
249876b614
support using previously declared types/localparams/params in package
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(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
Eddie Hung
5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings
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IdString: use more ID::*, make them easier to use, speed up IdString::in()
2020-04-02 11:47:25 -07:00
Eddie Hung
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
Claire Wolf
c69f4b246a
Merge pull request #1846 from dh73/ast_fe
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Adding error message for when size (width) of number literal is zero
2020-04-02 18:15:15 +02:00
Eddie Hung
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
David Shah
c3997c77a5
verilog: Add location info for generate constructs
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-01 18:47:20 +01:00
Diego H
c859bcf71b
Replacing log_error for log_file_error due consistency
2020-03-31 12:01:29 -06:00
Diego H
92809bb1d3
Adding error message for when size (width) of number literal is zero
2020-03-30 17:18:13 -06:00
N. Engelhardt
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope
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Support module/package/interface/block scope for typedef names.
2020-03-30 13:55:39 +02:00
Peter Crozier
f8c065ed1c
Inline productions to follow house style.
2020-03-27 16:21:45 +00:00
Rupert Swarbrick
044ca9dde4
Add support for SystemVerilog-style `define to Verilog frontend
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This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
Peter Crozier
9a8a644ad1
Error duplicate declarations of a typedef name in the same scope.
2020-03-24 14:35:21 +00:00
Peter Crozier
ecc22f7fed
Support module/package/interface/block scope for typedef names.
2020-03-23 20:07:22 +00:00
Peter Crozier
c06eda2504
Build pkg_user_types before parsing in case of changes in the design.
2020-03-22 18:20:46 -07:00
Peter
0aaa36ca6d
Clear pkg_user_types if no packages following a 'design -reset-vlog'.
2020-03-22 18:20:46 -07:00
Peter
14f32028ec
Parser changes to support typedef.
2020-03-22 18:20:46 -07:00
Miodrag Milanović
d46259becd
Merge pull request #1787 from YosysHQ/mmicko/lexer_deps
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Add dependency to verilog_lexer.cc
2020-03-19 18:24:40 +01:00
Miodrag Milanovic
dc75ed7dac
Add one mode dependency
2020-03-19 16:53:40 +01:00
N. Engelhardt
b473264a06
Merge pull request #1775 from huaixv/asserts_locations
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Add precise locations for asserts
2020-03-19 13:12:18 +01:00
huaixv
cd82ccd258
Add precise locations for asserts
2020-03-19 10:22:07 +08:00
Alberto Gonzalez
6dd2024965
Add AST node source location information in a couple more parser rules.
2020-03-17 06:22:12 +00:00
Miodrag Milanović
569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux
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refixed parsing of constant with comment between size and value
2020-03-14 13:34:59 +02:00
Marcus Comstedt
5e94bf0291
refixed parsing of constant with comment between size and value
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The three parts of a based constant (size, base, digits) are now three
separate tokens, allowing the linear whitespace (including comments)
between them to be treated as normal inter-token whitespace.
2020-03-11 18:21:44 +01:00
Eddie Hung
2d63bf5877
verilog: also set location for simple_behavioral_stmt
2020-03-10 10:29:24 -07:00
Alberto Gonzalez
da8270aa01
Set AST source locations in more parser rules.
2020-03-10 01:50:39 +00:00
Claire Wolf
a7cc4673c3
Fix partsel expr bit width handling and add test case
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-08 16:12:12 +01:00
Claire Wolf
d59da5a4e4
Fix bison warning for "pure-parser" option
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-03 08:41:55 -08:00
Alberto Gonzalez
f0afd65035
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
Eddie Hung
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
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Improve specify parser
2020-02-21 09:15:17 -08:00
Claire Wolf
cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
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Enum support
2020-02-20 18:17:25 +01:00
Eddie Hung
ea4bd161b6
verilog: add support for more delays than just rise/fall
2020-02-19 11:09:37 -08:00
Jeff Wang
d12ba42a74
add attributes for enumerated values in ilang
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- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
2020-02-17 04:42:42 -05:00
Eddie Hung
d20c1dac73
verilog: ignore ranges too without -specify
2020-02-13 17:58:43 -08:00
Eddie Hung
6b58c1820c
verilog: improve specify support when not in -specify mode
2020-02-13 13:27:15 -08:00
Eddie Hung
2e51dc1856
verilog: ignore '&&&' when not in -specify mode
2020-02-13 13:06:13 -08:00
Eddie Hung
b523ecf2f4
specify: system timing checks to accept min:typ:max triple
2020-02-13 12:42:15 -08:00
N. Engelhardt
e069259a53
Merge pull request #1679 from thasti/delay-parsing
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Fix crash on wire declaration with delay
2020-02-13 12:01:27 +01:00
Stefan Biereigel
b844b078db
correct wire declaration grammar for #1614
2020-02-03 21:29:40 +01:00
David Shah
4bfd2ef4f3
sv: Improve handling of wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
5df591c023
hierarchy: Resolve SV wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
50f86c11b2
sv: Add lexing and parsing of .* (wildcard port conns)
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
Jeff Wang
cc2236d0c0
lexer doesn't seem to return TOK_REG for logic anymore
2020-01-16 18:08:58 -05:00
Jeff Wang
5ddf84d430
allow enum typedefs
2020-01-16 17:17:42 -05:00
Jeff Wang
16ea4ea61a
partial rebase of PeterCrozier's enum work onto current master
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I tried to keep only the enum-related changes, and minimize the diff. (The
original commit also had a lot of work done to get typedefs working, but yosys
has diverged quite a bit since the 2018-03-09 commit, with a new typedef
implementation.) I did not include the import related changes either.
Original commit:
"Initial implementation of enum, typedef, import. Still a WIP."
881833aa73
2020-01-16 13:51:47 -05:00
Rodrigo Alejandro Melo
e9dc2759c4
Fixed some missing "verilog_" in documentation
2019-12-13 10:17:05 -03:00
whitequark
e97e33d00d
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
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Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.
Also fix the Verilog frontend to never emit such constructs.
2019-12-04 11:59:36 +00:00