Commit Graph

1570 Commits

Author SHA1 Message Date
Martin Povišer 134eb15c7e celledges: Clean up shift rules 2024-01-19 11:08:31 +01:00
Catherine a33acb7cd9 cxxrtl: refactor the formatter and use a closure.
This commit achieves three roughly equally important goals:
1. To bring the rendering code in kernel/fmt.cc and in cxxrtl.h as close
   together as possible, with an ideal of only having the bigint library
   as the difference between the render functions.
2. To make the treatment of `$time` and `$realtime` in CXXRTL closer to
   the Verilog semantics, at least in the formatting code.
3. To change the code generator so that all of the `$print`-to-`string`
   conversion code is contained inside of a closure.

There are two reasons to aim for goal (3):
a. Because output redirection through definition of a global ostream
   object is neither convenient nor useful for environments where
   the output is consumed by other code rather than being printed on
   a terminal.
b. Because it may be desirable to, in some cases, ignore the `$print`
   cells that are present in the netlist based on a runtime decision.
   This is doubly true for an upcoming `$check` cell implementing
   assertions, since failing a `$check` would by default cause a crash.
2024-01-16 16:35:51 +00:00
hakan-demirli e093f57c10 fix: fail if neither HOME nor XDG_STATE_HOME are set 2024-01-08 08:49:04 +03:00
hakan-demirli 54c3b63d24 fix: third time is the charm 2024-01-07 14:34:27 +03:00
hakan-demirli 31b45c9555 fix: xdg spec for hist 2024-01-07 14:17:48 +03:00
hakan-demirli bcf1c7b879
Merge branch 'YosysHQ:master' into master 2024-01-07 14:08:35 +03:00
Martin Povišer a96c257b3f celledges: Add messy rules that do pass the tests
This passes `test_cell -edges` on all the types of shift cells.
2024-01-04 19:34:15 +01:00
Claire Xenia Wolf fb72dc1a40 Add constexpr hashlib default constructors
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2023-12-29 19:20:44 +01:00
hakan-demirli f50e8a3c1b Follow the XDG Base Directory Specification 2023-12-21 21:44:02 +03:00
Krystine Sherwin afe8eff790
Merge updated master into krys/docs 2023-12-13 10:17:25 +13:00
Martin Povišer 4cce491639 celledges: s/x_jump/zpad_jump/ 2023-12-10 00:27:42 +01:00
Martin Povišer 80b8cd19c4 rtlil: Fix value type for iterator over `SigSpec`
When we are iterating over a `SigSpec`, the visited values will be of
type `SigBit` (as is the return type of `operator*()`). Account for that
in the publicly declared types.
2023-12-09 19:01:39 +01:00
Martin Povišer 189064b8da rtlil, hashlib: Remove deprecated `std::iterator` usage
`std::iterator` has been deprecated in C++17. Yosys is being compiled
against the C++11 standard but plugins can opt to compile against a
newer one. To silence some deprecation warnings when those plugins are
being compiled, replace the `std::iterator` inheritance with the
equivalent type declarations.
2023-12-09 19:01:39 +01:00
N. Engelhardt beaae79e73
Merge pull request #4021 from povik/booth-wallace
Change `booth` architecture for improved delay, similar signed/unsigned results
2023-11-27 16:26:03 +01:00
Martin Povišer 84568453f8 rtlil: Add `lsb()` `msb()` SigSpec helpers 2023-11-22 12:46:15 +01:00
Martin Povišer 282ce24eec fmt: Handle free-standing time arguments 2023-11-20 17:25:42 +01:00
Jannis Harder 6cf50d16a8
Merge pull request #3973 from anonkey/master
cli(tcl): add ability to pass argument to tcl script from cli
2023-11-13 16:29:05 +01:00
Jannis Harder d415b4d98a cli: Cleanups for tcl argument handling
* Keep the previous behavior when no tcl script is used
* Do not treat "-" as a flag but as a positional argument
* Keep including <unistd.h> as it's also used for other functions (at
  least for the emscripten build)
* Move the custom getopt implementation into the Yosys namespace to
  avoid potential collisions
2023-11-06 16:40:13 +01:00
N. Engelhardt 93a426cbbf
Merge pull request #4008 from nakengelhardt/mem_libmap_data_attr
memory_libmap: look for ram_style attributes on surrounding signals
2023-11-06 16:25:38 +01:00
anonkey ea91f189a3
cli(tcl): add ability to pass argument to tcl script from cli 2023-11-03 12:21:35 +01:00
Miodrag Milanovic 4eb18e1f07 change verific log callback api 2023-11-01 08:13:27 +01:00
Krystine Sherwin 8fad77bd0f
Merge branch 'master' into krys/docs
Fix failing verific tests
2023-11-01 13:17:51 +13:00
N. Engelhardt f9ab6e147a mem: only import attributes from ports if the memory doesn't have them yet 2023-10-30 16:31:53 +01:00
N. Engelhardt 1b6d1e9419 memory_libmap: look for ram_style attributes on surrounding signals 2023-10-19 19:23:35 +02:00
Lofty d21c464ae4
Merge pull request #3946 from rmlarsen/toposort
Speed up TopoSort by 2.7-3.3x.
2023-10-17 13:00:18 +01:00
Martin Povišer bdd74e61ae celledges: Account for shift down of x-bits wrt B port 2023-10-16 13:29:47 +02:00
N. Engelhardt 6c562c76bc fix handling right shifts 2023-10-12 11:46:09 +02:00
N. Engelhardt 2d6d6a8da1 fix handling a_width != y_width 2023-10-12 11:46:09 +02:00
N. Engelhardt d0e559a34f celledges: support shift ops 2023-10-12 11:46:09 +02:00
N. Engelhardt 3e22791810
Merge pull request #3975 from rmlarsen/optmerge 2023-10-09 17:05:19 +02:00
Rasmus Munk Larsen bc0df04e06 Get rid of double lookup in TopoSort::node(). This speeds up typical TopoSort time overall by ~10%. 2023-10-06 12:53:05 -07:00
Miodrag Milanovic 2ab7d1d0c8 Fix readline/editline memory leak 2023-10-06 16:05:44 +02:00
Rasmus Munk Larsen 6a5799cc2e Add missing initialization of node_cmp_ member. 2023-10-05 17:27:26 -07:00
Rasmus Munk Larsen 0a37c2a301 Fix translation bug: The old code really checks for the presense of a node, not an edge in glift and flatten.
Add back statement that inserts nodes in order in opt_expr.cc.
2023-10-05 17:01:42 -07:00
Rasmus Munk Larsen fd7bd420b3 Add back newline. 2023-10-05 15:26:29 -07:00
Rasmus Munk Larsen e38c9e01c9 Undo formatting changes in kernel/utils.h. 2023-10-05 15:24:26 -07:00
Rasmus Munk Larsen 8e0308b5e7 Revert changes to celltypes.h. Use dict instead of std::unordered_map and most hash function for uint64_t to hashlib.h to support this. 2023-10-03 14:25:59 -07:00
Rasmus Munk Larsen 7b454d4633 Revert changes to celltypes.h. 2023-10-03 14:06:41 -07:00
Rasmus Munk Larsen a6247cba42 Fix compiler warnings from GCC. 2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen cb9f318d37 Remove local modifications. 2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen ff915d21b6 Update comment. 2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen 4968229efc Speed up stringf / vstringf by 1.8x.
The main speedup is accomplished by avoiding a heap allocation in the common case where the final string length is less than 128. Inlining stringf & vstringf adds an additional improvement.
2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen 058973faee Undo formatting change. 2023-10-02 16:15:47 -07:00
Rasmus Munk Larsen bce984fa60 Speed up OptMergePass by 1.7x.
The main speedup comes from swithing from using a SHA1 hash to std::hash<std::string>. There is no need to use an expensive cryptographic hash for fingerprinting in this context.
2023-10-02 15:57:18 -07:00
Martin Povišer b894abf8b1
Merge pull request #3959 from rmlarsen/decode_string
Speed up RTLIL::Const::decode_string by 1.7x.
2023-10-02 16:38:43 +02:00
N. Engelhardt dcb600ab81
Merge pull request #3938 from povik/booth-cleanup 2023-10-02 16:10:17 +02:00
Rasmus Munk Larsen 12218a4c74 Unflip i and j. 2023-09-28 19:39:09 -07:00
Rasmus Munk Larsen 01a015747e Speed up RTLIL::Const::decode_string by 1.7x. 2023-09-27 17:16:13 -07:00
Wanda c172fef01a hashlib: Use a better hash for pool. 2023-09-26 18:55:06 +01:00
Martin Povišer d641dfaec2 rtlil: Add helper to emit full-adder cells 2023-09-25 14:50:41 +02:00
Ethan Mahintorabi aa06809d64 rtlil: Speeds up Yosys by 17%
This PR speeds up by roughly 17% across a wide spectrum of designs
tested at Google. Particularly for the mux generation pass.

Co-authored-by: Rasmus Larsen <rmlarsen@google.com>
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2023-09-21 10:46:11 +01:00
Rasmus Munk Larsen b9745f638b Remove extraneous "public:". 2023-09-20 16:20:08 -07:00
Rasmus Munk Larsen e0042bdff7 Speed up TopoSort. The main sorting algorithm implementation in TopoSort::sort_worker is 11-12x faster. Overall, the complete sequence of building the graph and sorting is about 2.5-3x faster. The overall impact in e.g. the replace_const_cells optimization pass is a ~25% speedup. End-to-end impact on our synthesis flow is about 3%. 2023-09-20 15:49:05 -07:00
Krystine Sherwin 98d0e749d6
Merge updates from 'master' into krys/docs 2023-09-19 11:28:36 +12:00
Jannis Harder 62b4df4989 dft_tag: Implement `$overwrite_tag` and `$original_tag`
This does not correctly handle an `$overwrite_tag` on a module output,
but since we currently require the user to flatten the design for
cross-module dft, this cannot be observed from within the design, only
by manually inspecting the signals in the design.
2023-09-13 11:32:36 +02:00
Miodrag Milanovic 27ac912709 Support import of $future_ff 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 54050a8c16 Basic support for tag primitives 2023-09-13 11:32:36 +02:00
Martin Povišer 05f0262d77
Merge pull request #3929 from YosysHQ/gatecat/fmt-fix
fmt: Fix C++ string assertion when buf is empty
2023-09-12 19:44:17 +02:00
gatecat 98b9459535 fmt: Fix C++ string assertion when buf is empty
Signed-off-by: gatecat <gatecat@ds0.me>
2023-09-12 18:12:07 +02:00
Martin Povišer cbc4ec8178 mem: Fix index confusion in write port merging
Fix mistaking the read-port and write-port indices for each other when
we are adding the partial transparency emulation to be able to merge two
write ports.
2023-09-12 16:43:59 +02:00
Martin Povišer 6d9cd16fad cellaigs: Drop initializer list in call to `IdString::in`
Remove superfluous curly braces in call to IdString::in to address
a compilation error (reproduced below) under GCC 9 and earlier.

kernel/cellaigs.cc:395:18: error: call to member function 'in' is ambiguous
if (cell->type.in({ID($gt), ID($ge)}))
~~~~~~~~~~~^~
./kernel/rtlil.h:383:8: note: candidate function
bool in(const std::string &rhs) const { return *this == rhs; }
^
./kernel/rtlil.h:384:8: note: candidate function
bool in(const pool &rhs) const { return rhs.co...
^
2023-08-14 11:42:19 +02:00
Charlotte f9d38253c5 ast: add `PRIORITY` to `$print` cells 2023-08-11 04:46:52 +02:00
Charlotte 7f7c61c9f0 fmt: remove lzero by lowering during Verilog parse
See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.
2023-08-11 04:46:52 +02:00
Charlotte 3571bf2c2d fmt: fuzz, remove some unnecessary busywork
Removing some signed checks and logic where we've already guaranteed the
values to be positive.  Indeed, in these cases, if a negative value got
through (per my realisation in the signed fuzz harness), it would cause
an infinite loop due to flooring division.
2023-08-11 04:46:52 +02:00
Charlotte 9f9561379b fmt: format %t consistently at initial 2023-08-11 04:46:52 +02:00
Charlotte 75b44f21d1 fmt: rudimentary %m support (= %l) 2023-08-11 04:46:52 +02:00
Charlotte c382d7d3ac fmt: %t/$time support 2023-08-11 04:46:52 +02:00
Charlotte b0f69f2cd5 tests: test cxxrtl against iverilog (and uncover bug!) 2023-08-11 04:46:52 +02:00
Charlotte 095b093f4a cxxrtl: first pass of $print impl 2023-08-11 04:46:52 +02:00
Charlotte d9e4582558 fmt: handle part with unspecified padding in `emit_rtlil`
e.g. `$displayh(8'ha)` won't have a padding set, because it just gets
`lzero` set instead by `compute_required_decimal_places`.

It also doesn't have a width.  In this case, we can just fill in a dummy
(unused) padding.  Either space or zero would work, but space is a bit
more distinct given the width field follows.

Also omit writing the width if it's zero.  This makes the emitted ilang
a little cleaner in places; `{8:> h0u}` is the output for this example,
now.  The other possible extreme would be `{8:>00h0u}`.
2023-08-11 04:46:52 +02:00
Charlotte 1a222cb163 fmt: function name typo 2023-08-11 04:46:52 +02:00
Charlotte 289f8d42cb fmt: correct parsing of {{ and }} for brace literals 2023-08-11 04:46:52 +02:00
Charlotte 3c8f84b70b fmt: fix another overrun 2023-08-11 04:46:52 +02:00
Charlotte 28bd3a4b5d fmt: don't overrun fmt string buffer
For input like "{", "{1", etc., we would exit the loop due to
`i < fmt.size()` no longer being the case, and then check if
`++i == fmt.size()`.  That would increment i to `fmt.size() + 1`,
and so execution continues.

The intention is to move i beyond the ':', so we do it only in that
case instead.
2023-08-11 04:46:52 +02:00
Charlotte 9db73aa872 celltypes: add `$print`
Otherwise, the \TRG connection is pruned by CleanZeroWidthPass.
2023-08-11 04:46:52 +02:00
whitequark d5c9953c09 ast: translate $display/$write tasks in always blocks to new $print cell. 2023-08-11 04:46:52 +02:00
whitequark 9ea241711e kernel: add format string helpers, `fmt`. 2023-08-11 04:46:52 +02:00
Krystine Sherwin 8203a01ba9
Adding custom domain for cmdref 2023-08-08 11:51:57 +12:00
Jannis Harder 0a3f805daa
Merge pull request #3840 from povik/cellaigs-cmp-cells 2023-07-31 16:23:39 +02:00
dragonmux ef7e358576
kernel/rtlil: Trailing whitespace cleanup 2023-07-26 20:50:55 +01:00
dragonmux b59c717245
kernel/rtlil: Fixed the destruction guard for IdString
The guard is optimised out on some compilers under certain conditions (eg: LTO on GCC) as constant under C++ lifetime rules.
This is because the guard type's member is invalid to access (UB) after the type has been destroyed, resulting in
`destruct_guard.ok` being unable to be `false` according to the optimiser, based on the lifetime rules.

This patch still invokes UB (all accesses to the destroyed IdString instance are), but at least the optimiser
can't reason that destruct_guard_ok cannot be false and therefore it's safe to optimise out from its guard role.
2023-07-26 20:46:56 +01:00
Martin Povišer 3ec00cceaa cellaigs: Generate models for integer comparison cells
Add the case of $lt, $le, $gt, $ge to the code generating AIGs.
2023-07-25 11:45:18 +02:00
N. Engelhardt 5e8db7000c
Merge pull request #3839 from povik/python-log-newline 2023-07-24 16:28:02 +02:00
N. Engelhardt 43780c9812
Merge pull request #3838 from povik/various-cleanup 2023-07-24 16:24:23 +02:00
N. Engelhardt 2bc0d86de7
Merge pull request #3854 from povik/abits-wide_log2-assert 2023-07-24 16:20:51 +02:00
Martin Povišer 77d4b5230e ast: Move to a new helper method to print input errors
It's a repeating pattern to print an error message tied to an AST
node. Start using an 'input_error' helper for that. Among other
things this is beneficial in shortening the print lines, which tend
to be long.
2023-07-20 23:40:19 -04:00
Martin Povišer 6a553568c5 kernel/mem: Assert ABITS is not below wide_log2
Later in the check() code we check the bottom wide_log2 bits on the
address port are zeroed out. If the address port is too narrow, we crash
due to out of bounds access. Explicitly assert the address port is wide
enough, so we don't crash on input such as

    read_rtlil <<EOF
    module \top
      wire input 1 \clk

      memory width 8 size 2 \mem

      cell $memwr $auto$:1:$8
        parameter \PRIORITY 1'0
        parameter \CLK_POLARITY 1'1
        parameter \CLK_ENABLE 1'1
        parameter \MEMID "\\mem"
        parameter \ABITS 1'0
        parameter \WIDTH 6'010000
        connect \DATA 16'0000000000000000
        connect \ADDR { }
        connect \EN 16'0000000000000000
        connect \CLK \clk
      end
    end
    EOF
    memory
2023-07-19 16:50:59 +02:00
Martin Povišer 5584ce95db log: Detect newlines in Python log output
So that Python messages are annotated with timestamps too (if -t was
passed).
2023-07-10 13:19:20 +02:00
Martin Povišer 8839d7fa5a cellaigs: Fix the case of $_NMUX_ cells
Later on there's a

  if (cell->type == ID($_NMUX_))

but that code was unreachable until now.
2023-07-10 12:45:03 +02:00
Miodrag Milanovic 75cf79588e Add ability for user plugin to add new verific log callback 2023-06-12 10:01:01 +02:00
gatecat 52c8c28d2c Add recover_names pass to recover names post-mapping 2023-05-25 10:55:07 +02:00
Henner Zeller a3a8f7be38 Remove a statement without effect.
The return value of the min(...) call is never used.
Looks like some leftover from some previous implementation.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
2023-04-17 10:53:05 -07:00
Jannis Harder b08a880704 backends/rtlil: Do not shorten a value with z bits to 'x 2023-01-29 14:02:25 +01:00
Miodrag Milanović 8180cc4325
Merge pull request #3624 from jix/sim_yw
Changes to support SBY trace generation with the sim command
2023-01-23 16:55:17 +01:00
Miodrag Milanović 245884a101
Merge pull request #3629 from YosysHQ/micko/clang_fixes
Fixes for some of clang scan-build detected issues
2023-01-23 16:24:22 +01:00
Miodrag Milanovic 200ffdccc5 Call yosys_shutdown to properly cleanup plugins and tcl when expecting error 2023-01-20 16:09:42 +01:00
Miodrag Milanovic 6574553189 Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
Jannis Harder d6c7aa0e3d sim/formalff: Clock handling for yw cosim 2023-01-11 18:07:16 +01:00
Jannis Harder 7ddec5093f sim: Improvements and fixes for yw cosim
* Fixed $cover handling
  * Improved sparse memory handling when writing traces
  * JSON summary output
2023-01-11 18:07:16 +01:00
Jannis Harder 636b9f2705 Support for BTOR witness to Yosys witness conversion 2023-01-11 18:07:16 +01:00
Jannis Harder 3e25e61778 aiger: Use new JSON code for writing aiger witness map files 2023-01-11 18:07:16 +01:00
Jannis Harder 29461ade17 Add json.{h,cc} for pretty printing JSON
Avoids errors in trailing comma handling, broken indentation and
improper escaping that is common when building JSON by manually
concatenating strings.
2023-01-11 18:07:16 +01:00
Jannis Harder 1494cfff00 New kernel/yw.{h,cc} to support reading Yosys witness files
This contains parsing code as well as generic routines to associate the
hierarchical signals paths within a Yosys witness file to a loaded RTLIL
design, including support for memories.
2023-01-11 18:07:16 +01:00
Jannis Harder 5042600c0d xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundef
This adds the xprop_decoder attribute to bwmuxes that drive the original
unencoded signals. Setundef is changed to ignore the x inputs of these
bwmuxes, so that they survive the prep script of SBY's formal flow. This
is required to make simulation (via sim) using the prep model show the
decoded x signals instead of 0/1 values made up by the solver.
2023-01-11 18:07:16 +01:00
Jannis Harder 5abaa59080
Merge pull request #3537 from jix/xprop
New xprop pass
2023-01-11 16:26:04 +01:00
N. Engelhardt d742d063d4 remove template declaration that stops function from being used 2023-01-11 16:09:05 +01:00
Miodrag Milanovic 5801152779 Deprecate gcc-4.8 2023-01-11 09:54:19 +01:00
Miodrag Milanovic 40282576b0 Display error instead of assertion when pass exists 2023-01-09 17:02:56 +01:00
N. Engelhardt fcd1c68ab7 add note to help about how to chain commands 2023-01-02 16:10:28 +01:00
KrystalDelusion 11fe4d0862 Remove help outputs for tex
Also for old website.
2022-12-08 05:57:41 +13:00
Jannis Harder 6589accfa9 tcl: Update help message to mention 'tee -s' 2022-12-05 16:47:22 +01:00
Jannis Harder a43356cb04 tcl: Unset both result.json and result.string only before calling pass 2022-12-05 16:17:00 +01:00
Jannis Harder 0f7b8b8d23 tcl: Don't exit repl on recoverable command errors 2022-12-02 15:50:41 +01:00
Jannis Harder 5524d5185d tcl: Return scratchpad result.json and result.string as tcl objects
This makes it possible for yosys commands to return values when invoked
as tcl commands. Right now no commands natively support this, but the
tee command can be used with json output like this:

```tcl
set stat [yosys tee -q -s result.json stat -json -top top]
dict get $stat modules \\top num_cells_by_type \$pmux
```

Or with newline separated lists like this:

```tcl
split [yosys tee -q -s result.string select -list top] "\n"
```
2022-12-02 14:36:19 +01:00
Jannis Harder ed02d52f30 tee: Allow logging command output to a given scratchpad value 2022-12-02 14:36:19 +01:00
Jannis Harder 7203ba7bc1 Add bitwise `$bweqx` and `$bwmux` cells
The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
2022-11-30 18:24:35 +01:00
Jannis Harder b982ab4f59 satgen, simlib: Consistent x-propagation for `$pmux` cells
This updates satgen and simlib to use a `$pmux` model where the output
is fully X when the S input is not all zero or one-hot with no x bits.
2022-11-30 18:24:35 +01:00
Miodrag Milanovic b0469b3863 Fix tcl crash in case of error executing command 2022-11-30 15:54:31 +01:00
Jannis Harder ed0e14820e sat: Add -set-def-formal option to force defined $any* outputs 2022-11-28 14:50:52 +01:00
Miodrag Milanovic 2450e6be22 Add TCL interactive shell mode 2022-11-25 16:18:02 +01:00
KrystalDelusion a14dec79eb
Rst docs conversion (#3496)
Rst docs conversion
2022-11-15 12:55:22 +01:00
Emil J c75f12a989
Add missing memory width assert preventing division by zero (#3546) 2022-11-09 10:34:25 +01:00
Jannis Harder 68d52cb1b1 fstdata: Update past_data before end_time callback
Required to make the '-at' parameter work.
2022-11-07 12:32:23 +01:00
Jannis Harder 3477f2d00b fstdata: Handle square/angle bracket replacemnt, change memory handling
When writing VCDs smtbmc replaces square brackets with angle brackets to
avoid the issues with VCD readers misinterpreting such signal names.

For memory addresses it also uses angle brackets and hexadecimal
addresses, while other tools will use square brackets and decimal
addresses.

Previously the code handled both forms of memory addresses, assuming
that any signal that looks like a memory address is a memory address.
This is not the case when the user uses regular signals whose names
include square brackets _or_ when the verific frontend generates such
names to represent various constructs.

With this change all angular brackets are turned into square brackets
when reading the trace _and_ when performing a signal lookup. This means
no matter which kind of brackets are used in the design or in the VCD
signals will be matched. This will not handle multiple signals that are
the same apart from replacing square/angle brackets, but this will cause
issues during the VCD writing of smtbmc already.

It still uses the distinction between square and angle brackets for
memories to decide whether the address is hex or decimal, but even if
something looks like a memory and is added to the `memory_to_handle`
data, the plain signal added to `name_to_handle` is used as-is, without
rewriting the address.

This last change is needed to successfully match verific generated
signal names that look like memory addresses while keeping memories
working at the same time. It may cause regressions when VCD generation
was done with a design that had memories but simulation is done with a
design where the memories were mapped to registers. This seems like an
unusual setup, but could be worked around with some further changes
should this be required.
2022-11-07 12:30:08 +01:00
Claire Xenia Wolf fe438ca1ab Add missing log_dump_val_worker forward declarations
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-10-30 18:57:50 +01:00
Jannis Harder c77b7343d0 Consistent $mux undef handling
* Change simlib's $mux cell to use the ternary operator as $_MUX_
  already does
* Stop opt_expr -keepdc from changing S=x to S=0
* Change const eval of $mux and $pmux to match the updated simlib
  (fixes sim)
* The sat behavior of $mux already matches the updated simlib

The verilog frontend uses $mux for the ternary operators and this
changes all interpreations of the $mux cell (that I found) to match the
verilog simulation behavior for the ternary operator. For 'if' and
'case' expressions the frontend may also use $mux but uses $eqx if the
verilog simulation behavior is requested with the '-ifx' option.

For $pmux there is a remaining mismatch between the sat behavior and the
simlib behavior. Resolving this requires more discussion, as the $pmux
cell does not directly correspond to a specific verilog construct.
2022-10-24 12:03:01 +02:00
Claire Xenia Wolf be1a12595a Add missing log_dump handler for std::vector<>
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-10-20 13:50:25 +02:00
Jannis Harder ac906d15ce Add YOSYS_ABORT_ON_LOG_ERROR environment variable for debugging. 2022-10-07 15:02:33 +02:00
Miodrag Milanovic 883831bd24 Fix mingw build 2022-08-29 10:04:12 +02:00
Aki Van Ness 6717e02023
kernel: hashlib: cleaned up message about table size in cases where `sizeof(int) == 4`, (closes #3440) 2022-08-25 11:08:51 -04:00
N. Engelhardt e3eb114e75 use inttypes format specifiers 2022-08-25 13:36:51 +02:00
N. Engelhardt 7e92e80741 dump runtime information for passes to json 2022-08-25 13:36:51 +02:00
Jannis Harder a5e1d3b997 formalff: Set new replaced_by_gclk attribute on removed dff's clks
This attribute can be used by formal backends to indicate which clocks
were mapped to the global clock. Update the btor and smt2 backend which
already handle clock inputs to understand this attribute.
2022-08-16 13:37:30 +02:00
Jannis Harder c0063288d6 Add the $anyinit cell and the formalff pass
These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
2022-08-16 13:37:30 +02:00
Miodrag Milanovic 6c65ca4e50 Encode filename unprintable chars 2022-08-08 16:13:33 +02:00
Marcelina Kościelnicka a681904237 Assorted microoptimization speedups in core data structures. 2022-07-27 17:05:30 +02:00
Miodrag Milanović 29a5947bf8
Make all compile under OpenBSD (#3423)
Co-authored-by: Josuah Demangeon <me@josuah.net>
2022-07-27 14:16:46 +02:00
Miodrag Milanović f086da8bdf
Merge pull request #3392 from rockybulwinkle/rockybulwinkle-patch-1
Update tcl doc, yosys does not return data to tcl
2022-07-11 16:26:23 +02:00
Marcelina Kościelnicka 58c51b9a0b
Remove empty lines 2022-07-11 16:19:34 +02:00
Miodrag Milanovic 0098b32c6c using more portable formatting 2022-07-06 10:53:35 +02:00
rockybulwinkle ec2f8796bd
Update tcl doc, yosys does not return data to tcl
This pull request is to address YosysHQ/yosys#2980.

The documentation, as originally written, does not make it clear that yosys commands, when used within a tcl script, do not return any value to the tcl script.

This pull request notes this and offers a workaround via tee as noted in the issue.
2022-06-23 13:34:08 -05:00
Marcelina Kościelnicka 6b7efe12b7 Add a check for packed memory MEMID uniqueness 2022-06-13 19:23:55 +02:00
Henner Zeller 9c41b43191 Use compiler-generated default constructor for RTLIL::Const::Const
No need for a manual implementation.
While at it: have the constructor that takes a string take a
const string reference instead to avoid a copy.
2022-06-09 16:07:45 +01:00
Jacob Lifshay cd57c5adb3 smt2: Add smtlib2_comb_expr attribute to allow user-selected smtlib2 expressions 2022-06-02 22:37:29 -07:00
Marcelina Kościelnicka 3a0aa9c663 memory_dff: Add support for no_rw_check attribute. 2022-06-02 12:49:34 +02:00
Miodrag Milanović 197c9e04e8
Merge pull request #3333 from mohamed/feature/tmpdir
Observe $TMPDIR variable when creating tmp files
2022-05-27 16:51:16 +02:00
Miodrag Milanovic 08275a1569 Cleanup, and fix windows 2022-05-27 16:13:55 +02:00
Mohamed A. Bamakhrama 1822be8792 Observe $TMPDIR variable when creating tmp files
POSIX defines $TMPDIR as containing the pathname of the directory where
programs can create temporary files. On most systems, this variable points to
"/tmp". However, on some systems it can point to a different location.
Without respecting this variable, yosys fails to run on such systems.

Signed-off-by: Mohamed A. Bamakhrama <mohamed@alumni.tum.de>
2022-05-27 15:06:53 +02:00
Miodrag Milanovic 4316cdb603 Remove set but unused variable 2022-05-27 12:37:03 +02:00
Marcelina Kościelnicka 7c5dba8b77 Add memory_libmap pass. 2022-05-18 17:32:56 +02:00
Miodrag Milanović 7c64c70727
Merge pull request #3310 from robinsonb5-PRs/master
Now calls Tcl_Init after creating the interp, fixes clock format.
2022-05-17 09:33:20 +02:00
Alastair M. Robinson 6c6017c973 Use log_warning when Tcl_Init fails, report error with Tcl_ErrnoMsg. 2022-05-16 20:22:28 +01:00
Marcelina Kościelnicka 2858bb03cd Add opt_ffinv pass. 2022-05-13 23:02:30 +02:00
Marcelina Kościelnicka 990c9b8e11 Add proc_rom pass. 2022-05-13 00:37:14 +02:00
Alastair M. Robinson 83dbea1689 Now calls Tcl_Init after creating the interp, fixes clock format. 2022-05-10 18:48:54 +01:00
Miodrag Milanovic d8adbff72f Handle possible non-memory indexed data 2022-05-06 08:05:23 +02:00
Miodrag Milanovic 8b3657454b map memory location to wire value, if memory is converted to FFs 2022-05-04 13:08:16 +02:00
Miodrag Milanovic ad48639cdd Start restoring memory state from VCD/FST 2022-05-04 10:41:04 +02:00
Miodrag Milanovic 9c7deabf94 Ignore change on last edge 2022-04-22 15:24:02 +02:00
Miodrag Milanovic 2e47b61cc6 Proper scope naming from FST 2022-03-30 15:55:15 +02:00
Marcelina Kościelnicka 3bebe17e5d kernel/mem: Only use FF init in read-first emu for mem with init 2022-03-28 17:03:02 +02:00
NotAFile 349c0ff0a7 Add some more reserve calls to RTLIL::Const
This results in a slight ~0.22% total speedup synthesizing vexriscv
2022-03-25 18:38:00 +00:00
Miodrag Milanovic 55eed8df57 More verbose warnings 2022-03-18 14:47:35 +01:00
Miodrag Milanovic 1f3423cd7d Recognize registers and set initial state for them in tb 2022-03-16 14:35:39 +01:00
Miodrag Milanovic 8be09b5b24 VCD reader support by using external tool 2022-02-28 09:09:07 +01:00
Miodrag Milanovic fca168797e Fix for last clock edge data 2022-02-25 16:15:32 +01:00
Miodrag Milanovic 5f918803de Changed error message 2022-02-18 15:06:49 +01:00
Miodrag Milanovic fb22d7cdc4 Add support for various ff/latch cells simulation 2022-02-16 13:27:59 +01:00
Claire Xen 49545c73f7
Merge branch 'master' into clk2ff-better-names 2022-02-11 16:03:12 +01:00
Miodrag Milanović d7f7227ce8
Merge pull request #3185 from YosysHQ/micko/co_sim
Add co-simulation in sim pass
2022-02-07 16:36:43 +01:00
Miodrag Milanovic c0a156bcb4 Error detection for co-simulation 2022-02-04 11:11:36 +01:00
Miodrag Milanovic 6db23de7b1 bug fix and cleanups 2022-02-04 10:01:06 +01:00
Miodrag Milanovic 26de52fa09 Cleanup 2022-01-31 12:00:15 +01:00
Miodrag Milanovic 543feb75cb Display simulation time data 2022-01-31 10:52:47 +01:00
Marcelina Kościelnicka 93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Miodrag Milanovic cb12b7c4d8 ignore not found private signals 2022-01-28 14:20:16 +01:00
Miodrag Milanovic f0f3c81c56 preserve VCD mangled names 2022-01-28 14:10:39 +01:00
Miodrag Milanovic 72acce0c82 detect edges even when x 2022-01-28 13:53:27 +01:00
Miodrag Milanovic a8d03df173 cleanup 2022-01-28 12:54:16 +01:00
Miodrag Milanovic 4f75a2ca1b Do actual compare 2022-01-28 12:50:41 +01:00
Miodrag Milanovic 3e35de2be1 Add more options and time handling 2022-01-28 10:18:02 +01:00
Marcelina Kościelnicka bac750fb99 kernel/mem: Add read-first semantic emulation code. 2022-01-28 08:48:33 +01:00
Marcelina Kościelnicka 5e4c6915c9 kernel/mem: Add functions to emulate read port enable/init/reset signals. 2022-01-27 19:28:07 +01:00
Miodrag Milanovic 226dc659f0 Fix tabs/spaces 2022-01-26 16:39:51 +01:00
Miodrag Milanovic 8a02616465 Add fstdata helper class 2022-01-26 10:23:38 +01:00
Zachary Snow 66447e8faf logger: fix unmatched expected warnings and errors
- Prevent unmatched expected error patterns from self-matching
- Prevent infinite recursion on unmatched expected warnings
- Always print the error message for unmatched error patterns
- Add test coverage for all unmatched message types
- Add test coverage for excess matched logs and warnings
2022-01-04 13:39:34 -07:00
Catherine 5dadcc85b7
Merge pull request #3111 from whitequark/issue-3110
Fix null pointer dereference after failing to extract DFF from memory
2021-12-14 21:25:06 +00:00
Claire Xenia Wolf e1c7a9a647 Hotfix for run_shell auto-detection
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-12-14 21:38:58 +01:00
Catherine 48ed6d998b Fix null pointer dereference after failing to extract DFF from memory.
Fixes #3110.
2021-12-14 16:27:37 +00:00
Marcelina Kościelnicka 26f0f6bb0b Fix unused param warning with ENABLE_NDEBUG. 2021-12-12 01:22:28 +01:00
Claire Xenia Wolf ce08046f44 Added "yosys -r <topmodule>"
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-12-10 00:15:37 +01:00
Claire Xenia Wolf 0cbdb42dcd Use "read" command to parse HDL files from Yosys command-line
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-12-09 10:33:55 +01:00
Lofty 77327b2544 sta: very crude static timing analysis pass
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2021-11-25 17:20:27 +01:00
Miodrag Milanovic d5de2a0cdb Make it work on all 2021-11-05 10:51:58 +01:00
Miodrag Milanovic d67eb0eb1c Removed semicolon from macro 2021-11-05 09:57:37 +01:00
Marcelina Kościelnicka 0a0df8d38c dfflegalize: Refactor, add aldff support. 2021-10-27 14:14:01 +02:00
Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
2021-10-25 18:25:50 -07:00
Rupert Swarbrick bd16d01c0e Split out logic for reprocessing an AstModule
This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
2021-10-25 18:25:50 -07:00
Marcelina Kościelnicka 5cebf6a8ef Change implicit conversions from bool to Sig* to explicit.
Also fixes some completely broken code in extract_reduce.
2021-10-21 20:20:31 +02:00
Marcelina Kościelnicka dc8da76282 Fix a regression from #3035. 2021-10-08 15:44:07 +02:00
Marcelina Kościelnicka 4e70c30775 FfData: some refactoring.
- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
2021-10-07 04:24:06 +02:00
Marcelina Kościelnicka e7d89e653c Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka 63b9df8693 kernel/ff: Refactor FfData to enable FFs with async load.
- *_en is split into *_ce (clock enable) and *_aload (async load aka
  latch gate enable), so both can be present at once
- has_d is removed
- has_gclk is added (to have a clear marker for $ff)
- d_is_const and val_d leftovers are removed
- async2sync, clk2fflogic, opt_dff are updated to operate correctly on
  FFs with async load
2021-10-02 20:19:48 +02:00
Marcelina Kościelnicka ec2b5548fe Add $aldff and $aldffe: flip-flops with async load. 2021-10-02 18:12:52 +02:00
Marcelina Kościelnicka f9aad606ca simplemap: refactor to use FfData. 2021-10-02 03:24:57 +02:00
Claire Xenia Wolf 4708907be8 Add additional check to SigSpec
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-09-10 16:51:34 +02:00
Marcelina Kościelnicka 10f8b75dca kernel/mem: Remove old parameter when upgrading $mem to $mem_v2.
Fixes #2967.
2021-08-16 13:31:27 +02:00
Rupert Swarbrick ee2b5b7ed1 Generate an RTLIL representation of bind constructs
This code now takes the AST nodes of type AST_BIND and generates a
representation in the RTLIL for them.

This is a little tricky, because a binding of the form:

    bind baz foo_t foo_i (.arg (1 + bar));

means "make an instance of foo_t called foo_i, instantiate it inside
baz and connect the port arg to the result of the expression 1+bar".
Of course, 1+bar needs a cell for the addition. Where should that cell
live?

With this patch, the Binding structure that represents the construct
is itself an AST::AstModule module. This lets us put the adder cell
inside it. We'll pull the contents out and plonk them into 'baz' when
we actually do the binding operation as part of the hierarchy pass.

Of course, we don't want RTLIL::Binding to contain an
AST::AstModule (since kernel code shouldn't depend on a frontend), so
we define RTLIL::Binding as an abstract base class and put the
AST-specific code into an AST::Binding subclass. This is analogous to
the AST::AstModule class.
2021-08-13 17:11:35 -06:00
Marcelina Kościelnicka c58ac63c97 logger: Add -check-expected subcommand.
This allows us to have multiple "expect this warning" calls in a single
long script, covering only as many passes as necessary.
2021-08-12 17:41:39 +02:00
Marcelina Kościelnicka fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka e6f3d1c225 kernel/mem: Introduce transparency masks. 2021-08-11 00:04:16 +02:00
Marcelina Kościelnicka d25b9088c8 Refactor common parts of SAT-using optimizations into a helper.
This also aligns the functionality:

- in all cases, the onehot attribute is used to create appropriate
  constraints (previously, opt_dff didn't do it at all, and share
  created one-hot constraints based on $pmux presence alone, which
  is unsound)
- in all cases, shift and mul/div/pow cells are now skipped when
  importing the SAT problem (previously only memory_share did this)
  — this avoids creating clauses for hard cells that are unlikely
  to help with proving the UNSATness needed for optimization
2021-08-09 16:54:35 +02:00
Marcelina Kościelnicka 19720b970d memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka 8bf9cb407d kernel/mem: Add a coalesce_inits helper.
While this helper is already useful to squash sequential initializations
into one in cxxrtl, its main purpose is to squash overlapping masked memory
initializations (when they land) and avoid having to deal with them in
cxxrtl runtime.
2021-07-13 15:59:11 +02:00
Marcelina Kościelnicka 0565c642a0 kernel/mem: Use delayed removal for inits as well. 2021-07-12 18:28:20 +02:00
Marcelina Kościelnicka 6d7d9ab077 kernel/mem: Add documentation for more helper functions. 2021-07-12 18:28:08 +02:00
Marcelina Kościelnicka 7f12820b26 kernel/mem: Commit new values of attributes in emit. 2021-07-12 13:39:31 +02:00
Marcelina Kościelnicka c86a79bf0b kernel/mem: Make the Mem helpers inherit from AttrObject. 2021-07-12 02:51:08 +02:00
Marcelina Kościelnicka 009940f56c rtlil: Make Process handling more uniform with Cell and Wire.
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
2021-07-12 00:47:34 +02:00
whitequark 02b4e67549 Fix WASI build after commit 1d88bea1. 2021-06-19 02:59:57 +00:00
gatecat 1d88bea18b pyosys: Clear SIGINT handler after Python loads
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-16 12:34:36 +01:00
Zachary Snow b516c681fe macos: fix leak in proc_self_dirname() 2021-06-14 12:33:26 -04:00
Rupert Swarbrick 081111714e Simplify some RTLIL destructors
No change in behaviour, but use range-based for loops instead of
iterators.
2021-06-14 12:06:08 -04:00
Marcelina Kościelnicka 1667ad658b opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.
The previous code, in addition to being needlessly limitted to 32 bits
in the first place, also had UB for the 31th bit (doing 1 << 31).
2021-06-09 19:53:44 +02:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka 6d5d845788 kernel/mem: Recognize some deprecated memory port configs.
Transparency is meaningless for asynchronous ports, so we assume
transparent == false to simplify the code in this case.  Likewise,
enable is meaningless, and we assume it is const-1.  However,
turns out that nMigen emits the former, and Verilog frontend emits
the latter, so squash these issues when ingesting a $memrd cell.

Fixes #2811.
2021-06-01 03:18:02 +02:00
Marcelina Kościelnicka cbf6b719fe Make a few passes auto-call Mem::narrow instead of rejecting wide ports.
This essentially adds wide port support for free in passes that don't
have a usefully better way of handling wide ports than just breaking
them up to narrow ports, avoiding "please run memory_narrow" annoyance.
2021-05-28 00:40:56 +02:00
Marcelina Kościelnicka b019db1f37 kernel/mem: Add helpers for write port widening. 2021-05-27 14:32:51 +02:00
Marcelina Kościelnicka 83a218141c kernel/mem: Add sub_addr helpers. 2021-05-26 03:34:02 +02:00
Marcelina Kościelnicka 57ca51be76 kernel/mem: Add prepare_wr_merge helper. 2021-05-26 02:55:00 +02:00
Marcelina Kościelnicka d99fce3bc7 mem/extract_rdff: Fix "no FF made" edge case.
When converting a sync transparent read port with const address to async
read port, nothing at all needs to be done other than clk_enable change,
and thus we have no FF cell to return.  Handle this case correctly in
the helper and in its users.
2021-05-25 23:42:31 +02:00
Marcelina Kościelnicka 3514c92dc4 mem/extract_rdff: Add alternate transparency handling.
When extracting read register from a transparent port that has an
enable, reset, or initial value, the usual trick of putting a register
on the address instead of data doesn't work.  In this case, create soft
transparency logic instead.

When transparency masks land, this will also be used to handle ports
that are transparent to only a subset of write ports.
2021-05-25 21:38:23 +02:00
Marcelina Kościelnicka 24b880b2de kernel/mem: Add model support for read port init value and resets.
Like wide port support, this is still completely unusable, and support
in various passes will be gradually added later.  It also has no support
at all in the cell library, so attempting to create a read port with
a reset or initial value will cause an assert failure for now.
2021-05-25 20:06:00 +02:00
Marcelina Kościelnicka 097de6c5f8 mem/extract_rdff: Fix wire naming and wide port support. 2021-05-25 17:51:47 +02:00
Marcelina Kościelnicka 4858721637 kernel/mem: Add emulate_priority helper. 2021-05-25 12:25:58 +02:00
Marcelina Kościelnicka 35ee774ea8 kernel/mem: Add a Mem::narrow helper to split up wide ports. 2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka 8c1999aac1 kernel/mem: Emit support for wide ports in packed mode.
Since the packed cell doesn't actually support wide ports yet, we just
auto-narrow them on emit.  The future packed cell will add
RD_WIDE_CONTINUATION and WR_WIDE_CONTINUATION parameters so the
transform will be trivially reversible for proper serialization.
2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka ff9713dd86 kernel/mem: Add model for wide ports.
Such ports cannot actually be created or used yet, this just adds the
necessary plumbing in the helper.  Subsequent commits will gradually
add wide port support to various yosys passes.
2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka 95a39d3425 kernel/mem: Add priority_mask to model.
This is going to be used to store arbitrary priority masks in the
future.  Right now, it is not supported by our cell library, so the
priority_mask is computed from port order on helper construction,
and discarded when emitted.  However, this allows us to already convert
helper-using passes to the new model.
2021-05-25 00:38:20 +02:00
Marcelina Kościelnicka dbfd0b61e3 hashlib: Add a hash for bool. 2021-05-24 22:02:15 +02:00
Marcelina Kościelnicka afd5366fc2 extract_rdff: Add initvals parameter.
This is not used yet, but will be needed when read port reset/initial
value support lands.
2021-05-23 22:05:26 +02:00
Marcelina Kościelnicka 1eea06bcc0 Add new helper class for merging FFs into cells, use for memory_dff.
Fixes #1854.
2021-05-23 14:46:59 +02:00
Marcelina Kościelnicka c4cc888b2c kernel/rtlil: Extract some helpers for checking memory cell types.
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
2021-05-22 21:43:00 +02:00
Marcelina Kościelnicka c7076495f1 kernel/mem: Add a check() function. 2021-05-22 21:42:53 +02:00
Marcelina Kościelnicka ff9e0394b8 kernel/mem: defer port removal to emit() 2021-05-22 21:42:53 +02:00
Zachary Snow d6d5c2ef34 rtlil: add const accessors for modules, wires, and cells 2021-03-25 10:44:08 -04:00
N. Engelhardt d9ec35a526 split CodingReadme into multiple files 2021-03-22 19:16:25 +01:00
Miodrag Milanović 6a0d1e117d
Merge pull request #2681 from msinger/fix-issue2606
Fix check for bad std::regex
2021-03-19 08:47:07 +01:00
Xiretza 3aa10e90ba modtools: fix use-after-free of cell pointers in ModWalker
cell_inputs and cell_outputs retain cell pointers as their keys across
invocations of setup(), which may however be invalidated in the meantime
(as happens in e.g. passes/opt/share.cc:1432). A later rehash of the
dicts (caused by inserting in ModWalker::add_wire()) will cause them to
be dereferenced.
2021-03-18 13:50:13 +01:00
Michael Singer d05d47cc04 Fix check for bad std::regex (fixes #2606) 2021-03-17 23:35:26 +01:00